Abstract: In embodiments described herein, a memory architecture has an array of non-volatile memory cells and a pair of independently controlled voltage pumps. The pair of voltage pumps is coupled for supplying both positive and negative voltage biases to the memory array during program and erase operations, such that a sum of the magnitudes of the positive and negative voltage biases is applied across a storage node of an accessed memory cell.

Abstract: In embodiments described herein, a memory architecture has an array of non-volatile memory cells and a pair of independently controlled voltage pumps. The pair of voltage pumps is coupled for supplying both positive and negative voltage biases to the memory array during program and erase operations, such that a sum of the magnitudes of the positive and negative voltage biases is applied across a storage node of an accessed memory cell.

Abstract: A memory architecture is provided with an array of non-volatile memory cells arranged in rows and columns, and a sense amplifier coupled to at least one column within the array for sensing a data bit stored within one of the non-volatile memory cells. In order to provide accurate sensing, a reference current generator is provided and coupled to the sense amplifier. The reference current generator provides a first reference current having adjustable magnitude and adjustable slope, and a second reference current having adjustable magnitude, but constant slope. The first reference current is supplied to the sense amplifier for sensing the data bit. The second reference current is supplied to a control block for generating clock signals used to control sense amplifier timing.

Abstract: In embodiments described herein, a memory architecture has an array of non-volatile memory cells and a pair of independently controlled voltage pumps. The pair of voltage pumps is coupled for supplying both positive and negative voltage biases to the memory array during program and erase operations, such that a sum of the magnitudes of the positive and negative voltage biases is applied across a storage node of an accessed memory cell.

Abstract: A circuit for discharging a high voltage signal to a supply voltage line. In one embodiment, the circuit includes a first switch receiving the high voltage signal; a second switch having an input coupled with the output of the first switch; and a third switch having an input coupled with the output of the second switch and having an output coupled with the supply voltage line. In this embodiment, the high voltage signal discharges to the supply voltage line when the first, second, and third switches are on. The circuit may include a fourth switch for clamping the high voltage signal to ground. The fourth switch may have a control coupled with the output of the first switch along a discharge path such that when the high voltage signal is discharging and approaches a voltage level of approximately ground, the fourth switch automatically turns on and clamps the high voltage signal to ground level.

Abstract: A circuit for generating an output signal, such as a subword line signal, to one or more memory cells of a memory. In one embodiment, the circuit includes four transistors each with a separate select line. In one example, a first switch is provided and has an input coupled with a global word line input signal; a second switch has an input coupled with the output of the first switch at an output node; a third switch has an input coupled with the global word line input signal and the output of the third switch being coupled with the output of the first switch at the output node; and a fourth switch having an input coupled with the output of the third switch at the output node and the output of the fourth switch is coupled with the output of the second switch.

Abstract: A NAND stack array (95′) is placed within a well formed on a semiconductor substrate and includes a series array of memory cell transistors (10) whose threshold voltages can be electrically altered over a range of depletion values. When a cell within a certain NAND stack is selected for a read operation, a peripheral circuit drives selected gate word line to the well potential and drives the word lines of the other gates within the selected NAND stack to a potential at least equal in magnitude to the magnitude of the a reference voltage plus the threshold voltage of a memory cell in the programmed state.

Abstract: A circuit for shifting a signal from a first voltage level referenced to a first voltage reference, to a second voltage level referenced to a second voltage reference, while reducing the gate to source voltages on the output transistors. In one embodiment, the circuit includes six switches. A first switch receives the signal; a second switch receives an inverted representation of the signal; a third switch receives the output of the first switch; a fourth switch receives the output of the second switch; a fifth switch, referenced to the second voltage reference, has an input coupled with the output of the first switch and a control coupled with the output of the fourth switch; and a sixth switch, referenced to the second voltage reference, has an input coupled with the output of the second switch and has a control coupled with the output of the third switch.

Abstract: A bistable non-volatile latch circuit adapted to store a non-volatile binary data state during a program operation, and to assume one of two stable states in response to a recall operation that correspond uniquely to the data state has first and second circuit sections. The first circuit section has a first non-volatile current path with means to set the impedance of the first current path in a non-volatile manner. A first end of the first current path is connected to provide a logic output signal, which represents a binary logic state depending on a voltage applied to the a first signal input node. The set/reset signal to the first current path varies between at least the power source voltage and a program voltage that is negative with respect to the power source voltage. A second circuit section generates an output voltage on a second output node that represents a binary logic state opposite from the output states of the first circuit section.

Abstract: The present invention involves a charge pump including an input node coupled to receive an input voltage from a power voltage source and an oscillator unit generates a periodic enable regulator signal and a periodic reset signal. A regulator clock unit is coupled to the oscillator unit generating a precharge (PC) signal and a reset regulator signal in response to the enable regulator signal. A pump clock unit receives a master clock signal and generating a plurality of pump clock signals. A charge pump unit is coupled to the input node and is operatively controlled by the plurality of pump clock signals, and coupled to the an output terminal coupled to produce an output signal (VPUMP). A regulator unit is coupled to receive the VPUMP signal, the PC signal, the reference signal and the enable regulator signal, where the regulator unit is responsive to the enable regulator signal to operate in either a precharge mode or a regulation mode.

Abstract: A timing circuit produces a clock signal. An address buffer circuit receives and stores a first address in a first latch and a second address in a second latch asynchronously with respect to the clock signal. A memory control circuit associated with an array of memory cells accesses a first memory cell in the array corresponding to the first address in a first clocked access cycle, and accesses a second memory cell in the array corresponding to the second address in a second clocked access cycle. If a further address is asynchronously received before said second access cycle, the further address replaces the second address in the second latch.

Abstract: A NAND stack array (95') is placed within a well formed on a semiconductor substrate and includes a series array of memory cell transistors (10) whose threshold voltages can be electrically altered over a range of depletion values. When a cell within a certain NAND stack is selected for a read operation, a peripheral circuit drives selected gate word line to the well potential and drives the word lines of the other gates within the selected NAND stack to a potential at least equal in magnitude to the magnitude of the a reference voltage plus the threshold voltage of a memory cell in the programmed state.

Abstract: A bistable non-volatile latch circuit adapted to store a non-volatile binary data state during a program operation, and to assume one of two stable states in response to a recall operation that correspond uniquely to the data state has first and second circuit sections. The first circuit section has a first non-volatile current path with means to set the impedance of the first current path in a non-volatile manner. A first end of the first current path is connected to provide a logic output signal, which represents a binary logic state depending on a voltage applied to the a first signal input node. The set/reset signal to the first current path varies between at least the power source voltage and a program voltage that is negative with respect to the power source voltage. A second circuit section generates an output voltage on a second output node that represents a binary logic state opposite from the output states of the first circuit section.

Abstract: A bistable non-volatile latch circuit adapted to store a non-volatile binary data state during a program operation, and to assume one of two stable states in response to a power up operation that correspond uniquely to the data state has first and second circuit sections. The first circuit section has a first non-volatile current path with means to set the impedance of the first current path in a non-volatile manner. A first end of the first current path is connected to provide a logic output signal, which represents a binary logic state depending on a voltage applied to the a first signal input node. The set/reset signal to the first current path varies between at least the power source voltage and a program voltage that is negative with respect to the power source voltage. A second circuit section generates an output voltage on a second output node that represents a binary logic state opposite from the output states of the first circuit section.

Abstract: A non-volatile memory cell array using only a single level of polysilicon and a single level of metal has programmable single transistor memory cells on a semiconductor substrate of a first conductivity type, a well of a second conductivity type in the substrate, parallel bitlines oriented in a first direction, and reference line segments oriented in the first direction. Each reference line is paired with one of each bitline. The array also has parallel word lines oriented in a second direction to form an array of intersections with the pairs of bitline/reference line pairs, and a rewriteable single transistor memory cell at each intersection point.

Abstract: A method and structure for preventing over erasure in non-volatile memory cells uses simultaneous erase and program current injections which offset one another. These currents come from two separate injection points within the non-volatile memory transistor and are dominant at different points during the erase operation. The first occurring current erases the non-volatile device and the second prevents over erasure.

Abstract: A semiconductor integrated circuit to determine a passage of time that may include a time during which no electrical power is supplied to the circuit is disclosed. The circuit has a timing device that includes a memory storage dielectric material for trapping charge carriers and releasing the trapped charge carriers in a known manner over time. The timing device has an electrical parameter that is relatable to an electric field created by the trapped charge carriers. A charge injection circuit is provided for selectively injecting charge carriers into the memory storage dielectric material to create an initialized state, and a time reader circuit determines when the electrical parameter has reached a predetermined value that corresponds to a passage of a predetermined time. Preferably the timing device is an insulated gate field effect transistor in which the memory storage dielectric material is a dielectric material, such as SONOS or SNOS, between the gate and channel overlying at least the channel area.

Abstract: A transistor structure (10), memory array (150) using the transistor structure, and method for making it are presented. The memory array (150), on a semiconductor substrate (152), contains a plurality of substantially parallel bit lines (154,155). A plurality of channel regions in the substrate (152) are bounded in one direction by a sets of bit line pairs (154,155). A conductive field shield layer (160), over a first insulation layer (156), is patterned to provide electrical regions over the channel regions between the first alternate sets of the bit lines (154,155) to form isolation transistor structures when biased with respect to the substrate (152). The field shield layer (160) is patterned to expose the channel regions of the memory transistors (151, . . . , 151'") between second alternate sets of the bit lines (155,154). A second insulating layer (163) is formed over the field shield layer (160).

Abstract: An N-channel SNOS or SONOS type memory array (100) has programmable states with a negative, depletion mode threshold lower in magnitude than the supply voltage V.sub.CC when erased and a positive threshold when programmed. During reading, the supply voltage V.sub.CC is applied to the drain (16), while a positive voltage V.sub.R less than V.sub.CC -V.sub.ds,sat is applied to the source (14), where V.sub.ds,sat is the saturation voltage of the device. A reference voltage may also be applied to the substrate (11) during a read operation. Selected devices have V.sub.R applied to the gate (12), while inhibited devices have ground or the substrate potential V.sub.SS applied to the gate (12).

Abstract: A transistor structure (10), memory array (150) using the transistor structure, and method for making it are presented. The memory array (150), on a semiconductor substrate (152), contains a plurality of substantially parallel bit lines (154,155). A plurality of channel regions in the substrate (152) are bounded in one direction by a sets of bit line pairs (154,155). A conductive field shield layer (160), over a first insulation layer (156), is patterned to provide electrical regions over the channel regions between the first alternate sets of the bit lines (154,155) to form isolation transistor structures when biased with respect to the substrate (152). The field shield layer (160) is patterned to expose the channel regions of the memory transistors (151, . . . , 151'") between second alternate sets of the bit lines (155,154). A second insulating layer (163) is formed over the field shield layer (160).