Abstract: An anomaly detection device includes a processor and a non-transitory memory that stores a program. The processor executes the program to operate an anomaly detection device as an obtainer that obtains a first object detection result generated by a first object detection device that is included in a first apparatus which is a vehicle and detects an object in the vicinity of the first apparatus and a second object detection result generated by a second object detection device that is included in a second apparatus in the vicinity of the first apparatus and detects an object in the vicinity of the second apparatus; a determiner that determines whether at least one of the first apparatus or the second apparatus is being attacked, by comparing the first object detection result and the second object detection result; and an outputter that outputs a result of determination by the determiner.

Abstract: An electric lock control method includes: performing a first determination of whether a person is present in a predetermined region surrounding an electric lock, based on first information generated by an electronic device; when it is determined that a first person is present in the predetermined region in the performing of the first determination, performing a second determination of whether the first person is a person who is permitted to unlock the electric lock, based on second information related to movement of the first person; and controlling a state of the electric lock based on a result of the second determination, the state being a locked state or an unlocked state.

Abstract: A semiconductor storage according to an embodiment of the present disclosure includes two power source paths, and a connection path that connects the power source paths. Each of the power source paths includes a power gate transistor and a current source transistor which are coupled in series. The connection path connects ends of the respective power source paths on a side of the current source transistor. The semiconductor storage further includes a storage element, and a switch element inserted between the connection path and the storage element. A back gate is coupled to an internal node in the current source transistor provided in a low-side path of the two power source paths.

Abstract: A semiconductor storage according to an embodiment of the present disclosure includes two power source paths, and a connection path that connects the power source paths. Each of the power source paths includes a power gate transistor and a current source transistor which are coupled in series. The connection path connects ends of the respective power source paths on a side of the current source transistor. The semiconductor storage further includes a storage element, and a switch element inserted between the connection path and the storage element. A back gate is coupled to an internal node in the current source transistor provided in a low-side path of the two power source paths.

Abstract: Fuse data is supplied to each of a plurality of function blocks through a transfer path using shift registers. When the reliability of fuse elements is low, there is a possibility that a part of the fuse data may have an error. Further, when the transfer path of the fuse data is long, there is a possibility that a value of the fuse data may be inverted due to an influence of noises. Thus, a decoder is arranged in the transfer path of the fuse data, and encoded data is stored in the fuse elements. By performing error detection/correction in the decoder, the high reliability is assured with respect to chip operations and the like.

Abstract: Fuse data is supplied to each of a plurality of function blocks through a transfer path using shift registers. When the reliability of fuse elements is low, there is a possibility that a part of the fuse data may have an error. Further, when the transfer path of the fuse data is long, there is a possibility that a value of the fuse data may be inverted due to an influence of noises. Thus, a decoder is arranged in the transfer path of the fuse data, and encoded data is stored in the fuse elements. By performing error detection/correction in the decoder, the high reliability is assured with respect to chip operations and the like.

Abstract: Fuse data is supplied to each of a plurality of function blocks through a transfer path using shift registers. When the reliability of fuse elements is low, there is a possibility that a part of the fuse data may have an error. Further, when the transfer path of the fuse data is long, there is a possibility that a value of the fuse data may be inverted due to an influence of noises. Thus, a decoder is arranged in the transfer path of the fuse data, and encoded data is stored in the fuse elements. By performing error detection/correction in the decoder, the high reliability is assured with respect to chip operations and the like.

Abstract: Fuse data is supplied to each of a plurality of function blocks through a transfer path using shift registers. When the reliability of fuse elements is low, there is a possibility that a part of the fuse data may have an error. Further, when the transfer path of the fuse data is long, there is a possibility that a value of the fuse data may be inverted due to an influence of noises. Thus, a decoder is arranged in the transfer path of the fuse data, and encoded data is stored in the fuse elements. By performing error detection/correction in the decoder, the high reliability is assured with respect to chip operations and the like.

Abstract: Fuse data is supplied to each of a plurality of function blocks through a transfer path using shift registers. When the reliability of fuse elements is low, there is a possibility that a part of the fuse data may have an error. Further, when the transfer path of the fuse data is long, there is a possibility that a value of the fuse data may be inverted due to an influence of noises. Thus, a decoder is arranged in the transfer path of the fuse data, and encoded data is stored in the fuse elements. By performing error detection/correction in the decoder, the high reliability is assured with respect to chip operations and the like.

Abstract: A fuse and fuse latch includes first and second fuse and fuse latches each serving as a redundancy information storage circuit. Fuse elements and a fuse latch are provided in each of the first and second fuse and fuse latches. The first and second fuse and fuse latches each output latched data as serial data to a fuse data transfer control circuit. The fuse data transfer control circuit serving as a redundancy information creation circuit is configured of a counter and a data transfer control circuit. The data transfer control circuit combines data output from the first and second fuse and fuse latches, thereby to create new data.

Abstract: A sense amplifier is connected to a pair of bit lines to read/write data. A bit line equalizer equalizes the potentials of the pair of bit lines. A sense amplifier equalizer equalizes the potentials of two power supply nodes of the sense amplifier. The sense amplifier equalizer is constituted by two types of MOS transistors whose gate oxide films have different thicknesses. MOS transistors of one type are formed in a thick film type Tr area. MOS transistors of the other type are formed in a thick film type Tr area.

Abstract: A sense amplifier is connected to a pair of bit lines to read/write data. A bit line equalizer equalizes the potentials of the pair of bit lines. A sense amplifier equalizer equalizes the potentials of two power supply nodes of the sense amplifier. The sense amplifier equalizer is constituted by two types of MOS transistors whose gate oxide films have different thicknesses. MOS transistors of one type are formed in a thick film type Tr area. MOS transistors of the other type are formed in a thick film type Tr area.

Abstract: A sense amplifier is connected to a pair of bit lines to read/write data. A bit line equalizer equalizes the potentials of the pair of bit lines. A sense amplifier equalizer equalizes the potentials of two power supply nodes of the sense amplifier. The sense amplifier equalizer is constituted by two types of MOS transistors whose gate oxide films have different thicknesses. MOS transistors of one type are formed in a thick film type Tr area. MOS transistors of the other type are formed in a thick film type Tr area.

Abstract: A semiconductor device includes a prime memory cell array, a redundant memory cell array, a holding circuit, a group of access lines, and first and second controlling circuits. The prime memory cell array includes prime memory cells. The redundant memory cell array includes redundant memory cells. The holding circuit holds an address of a defective memory cell. The access lines are respectively connected to the redundant memory cells. The first controlling circuit supplies a substitution command to substitute a redundant memory cell for the defective memory cell corresponding to the address held in the holding circuit, through the group of access lines to the defective memory cell. The second controlling circuit, when a plurality of portions of the holding circuit holds the address of the defective memory cell, disables all but one of the plurality of portions which hold the address of the defective memory cell.

Abstract: Fuse data is supplied to each of a plurality of function blocks through a transfer path using shift registers. When the reliability of fuse elements is low, there is a possibility that a part of the fuse data may have an error. Further, when the transfer path of the fuse data is long, there is a possibility that a value of the fuse data may be inverted due to an influence of noises. Thus, a decoder is arranged in the transfer path of the fuse data, and encoded data is stored in the fuse elements. By performing error detection/correction in the decoder, the high reliability is assured with respect to chip operations and the like.

Abstract: A semiconductor device includes a prime memory cell array, a redundant memory cell array, a holding circuit, a group of access lines, and first and second controlling circuits. The prime memory cell array includes prime memory cells. The redundant memory cell array includes redundant memory cells. The holding circuit holds an address of a defective memory cell. The access lines are respectively connected to the redundant memory cells. The first controlling circuit supplies a substitution command to substitute a redundant memory cell for the defective memory cell corresponding to the address held in the holding circuit, through the group of access lines to the defective memory cell. The second controlling circuit, when a plurality of portions of the holding circuit holds the address of the defective memory cell, disables all but one of the plurality of portions which hold the address of the defective memory cell.

Abstract: A sense amplifier is connected to a pair of bit lines to read/write data. A bit line equalizer equalizes the potentials of the pair of bit lines. A sense amplifier equalizer equalizes the potentials of two power supply nodes of the sense amplifier. The sense amplifier equalizer is constituted by two types of MOS transistors whose gate oxide films have different thicknesses. MOS transistors of one type are formed in a thick film type Tr area. MOS transistors of the other type are formed in a thick film type Tr area.

Abstract: A semiconductor device includes a prime memory cell array, a redundant memory cell array, a holding circuit, a group of access lines, and first and second controlling circuits. The prime memory cell array includes prime memory cells. The redundant memory cell array includes redundant memory cells. The holding circuit holds an address of a defective memory cell. The access lines are respectively connected to the redundant memory cells. The first controlling circuit supplies a substitution command to substitute a redundant memory cell for the defective memory cell corresponding to the address held in the holding circuit, through the group of access lines to the defective memory cell. The second controlling circuit, when a plurality of portions of the holding circuit holds the address of the defective memory cell, disables all but one of the plurality of portions which hold the address of the defective memory cell.

Abstract: A semiconductor device includes first, second and third semiconductor circuits. The first semiconductor circuit has a first function. The second semiconductor circuit has a second function different from the first function. The third semiconductor circuit is provided in the second semiconductor circuit and has part of the first function. The third semiconductor circuit transmits/receives no signals to/from the second semiconductor circuit and operates independently of the second semiconductor circuit.

Abstract: A semiconductor device includes a prime memory cell array, a redundant memory cell array, a holding circuit, a group of access lines, and first and second controlling circuits. The prime memory cell array includes prime memory cells. The redundant memory cell array includes redundant memory cells. The holding circuit holds an address of a defective memory cell. The access lines are respectively connected to the redundant memory cells. The first controlling circuit supplies a substitution command to substitute a redundant memory cell for the defective memory cell corresponding to the address held in the holding circuit, through the group of access lines to the defective memory cell. The second controlling circuit, when a plurality of portions of the holding circuit holds the address of the defective memory cell, disables all but one of the plurality of portions which hold the address of the defective memory cell.