Abstract: A sense amplifier is connected to a pair of bit lines to read/write data. A bit line equalizer equalizes the potentials of the pair of bit lines. A sense amplifier equalizer equalizes the potentials of two power supply nodes of the sense amplifier. The sense amplifier equalizer is constituted by two types of MOS transistors whose gate oxide films have different thicknesses. MOS transistors of one type are formed in a thick film type Tr area. MOS transistors of the other type are formed in a thick film type Tr area.

Abstract: A semiconductor device includes a prime memory cell array, a redundant memory cell array, a holding circuit, a group of access lines, and first and second controlling circuits. The prime memory cell array includes prime memory cells. The redundant memory cell array includes redundant memory cells. The holding circuit holds an address of a defective memory cell. The access lines are respectively connected to the redundant memory cells. The first controlling circuit supplies a substitution command to substitute a redundant memory cell for the defective memory cell corresponding to the address held in the holding circuit, through the group of access lines to the defective memory cell. The second controlling circuit, when a plurality of portions of the holding circuit holds the address of the defective memory cell, disables all but one of the plurality of portions which hold the address of the defective memory cell.

Abstract: A semiconductor device includes first, second and third semiconductor circuits. The first semiconductor circuit has a first function. The second semiconductor circuit has a second function different from the first function. The third semiconductor circuit is provided in the second semiconductor circuit and has part of the first function. The third semiconductor circuit transmits/receives no signals to/from the second semiconductor circuit and operates independently of the second semiconductor circuit.

Abstract: A semiconductor device includes a prime memory cell array, a redundant memory cell array, a holding circuit, a group of access lines, and first and second controlling circuits. The prime memory cell array includes prime memory cells. The redundant memory cell array includes redundant memory cells. The holding circuit holds an address of a defective memory cell. The access lines are respectively connected to the redundant memory cells. The first controlling circuit supplies a substitution command to substitute a redundant memory cell for the defective memory cell corresponding to the address held in the holding circuit, through the group of access lines to the defective memory cell. The second controlling circuit, when a plurality of portions of the holding circuit holds the address of the defective memory cell, disables all but one of the plurality of portions which hold the address of the defective memory cell.

Abstract: A semiconductor device includes first, second and third semiconductor circuits. The first semiconductor circuit has a first function. The second semiconductor circuit has a second function different from the first function. The third semiconductor circuit is provided in the second semiconductor circuit and has part of the first function. The third semiconductor circuit transmits/receives no signals to/from the second semiconductor circuit and operates independently of the second semiconductor circuit.

Abstract: A semiconductor memory device comprises a data line shifting circuit for connecting a plurality of data lines and spare data lines to a plurality of I/O data lines, a plurality of I/O numbering circuits for assigning the I/O data lines shift indicating numbers as locational information, the shift indicating numbers incrementing by one for each start point for data line shifting executed by the data line shifting circuit, a selection circuit for storing the correlationship between defective column addresses and the shift indicating numbers and outputting a selection signal corresponding to the shift indicating numbers when a defective-column address is input, a shift control circuit for comparing the selection signal with the shift indicating numbers and outputting a shift control signal to the data line shifting circuit based on a result of the comparison, and a number setting selecting circuit for selectively using a plurality of I/O numbering circuits.

Abstract: On a semiconductor substrate, there are formed a first macro cell having wiring layers of three layers each formed of a metal wiring layer (for example, an aluminum wiring) and a second macro cell having wiring layers of three layers each formed of a metal wiring layer similar to the first macro cell. The first macro cell is formed to have a wiring structure of three wiring layers though the originally necessary number of metal wiring layers is two. The metal wiring layer of each layer on the first macro cell is formed of the same material as the metal wiring layer of the corresponding each layer on the second macro cell. Moreover, the metal wiring layer of each layer is formed to have the same film thickness. In order to connect the first and second macro cells to each other, a macro interconnection wiring is formed to be included in the third wiring layer (uppermost wiring layer).

Abstract: On a semiconductor substrate, there are formed a first macro cell having wiring layers of three layers each formed of a metal wiring layer (for example, an aluminum wiring) and a second macro cell having wiring layers of three layers each formed of a metal wiring layer similar to the first macro cell. The first macro cell is formed to have a wiring structure of three wiring layers though the originally necessary number of metal wiring layers is two. The metal wiring layer of each layer on the first macro cell is formed of the same material as the metal wiring layer of the corresponding each layer on the second macro cell. Moreover, the metal wiring layer of each layer is formed to have the same film thickness. In order to connect the first and second macro cells to each other, a macro interconnection wiring is formed to be included in the third wiring layer (uppermost wiring layer).

Abstract: A semiconductor memory device comprises: a memory cell array having memory cells arranged in the form of a matrix; a redundant column cell array configured to relieve a defective column of the memory cell array; a decoder circuit configured to decode an address to select a memory cell in the memory cell array; a plurality of data lines, to which data read out from the memory cell array or data to be written in the memory cell array, corresponding to a plurality of columns, is transferred by the decoder circuit; a data line, to which data read out from the redundant column cell array or data to be written in the redundant column cell array is transferred; a data line shift circuit configured to shift, one by one, data line and the spare data line, which are arranged on one side of a data line serving as a starting point, to which data of a defective column is to be transferred when the defective column is accessed, to connect the data line and the spare data lines to data input/output lines; a selecting circui

Abstract: A semiconductor memory device comprises a data line shifting circuit for connecting a plurality of data lines and spare data lines to a plurality of I/O data lines, a plurality of I/O numbering circuits for assigning the I/O data lines shift indicating numbers as locational information, the shift indicating numbers incrementing by one for each start point for data line shifting executed by the data line shifting circuit, a selection circuit for storing the correlationship between defective column addresses and the shift indicating numbers and outputting a selection signal corresponding to the shift indicating numbers when a defective-column address is input, a shift control circuit for comparing the selection signal with the shift indicating numbers and outputting a shift control signal to the data line shifting circuit based on a result of the comparison, and a number setting selecting circuit for selectively using a plurality of I/O numbering circuits.

Abstract: Column select lines for selecting a column in a memory cell array are provided near the memory cell array. Main column select sections including drivers are connected to one end of the column select lines. Latch circuits are connected to the other end of the column select lines. Receiving the output signal from the driver, the latch circuit, together with the driver, drives the column select line.

Abstract: A semiconductor integrated circuit device has memory cell arrays capable of using shared sense amplifiers, wherein memory can be increased by refresh units to a desired capacity. Specific memory cell arrays can be selected when writing/reading and refreshing by switching address signals when writing/reading and when refreshing. The number of word lines selected when refreshing is always uniform in the memory system.

Abstract: There is disclosed a memory cell array including regular and redundant memory cells, a plurality of bit lines connected to the regular memory cells, a plurality of redundant bit lines connected to the redundant memory cells, a regular data line commonly coupled to the plurality of regular bit lines, and a redundant data line commonly coupled to the plurality of redundant bit lines. Column selection lines include regular column selection lines for selecting regular bit lines, and redundant column selection lines for selecting redundant bit lines. Furthermore, the number of redundant column selection lines is smaller than that of the regular column selection lines.

Abstract: On a semiconductor substrate, there are formed a first macro cell having wiring layers of three layers each formed of a metal wiring layer (for example, an aluminum wiring) and a second macro cell having wiring layers of three layers each formed of a metal wiring layer similar to the first macro cell. The first macro cell is formed to have a wiring structure of three wiring layers though the originally necessary number of metal wiring layers is two. The metal wiring layer of each layer on the first macro cell is formed of the same material as the metal wiring layer of the corresponding each layer on the second macro cell. Moreover, the metal wiring layer of each layer is formed to have the same film thickness. In order to connect the first and second macro cells to each other, a macro interconnection wiring is formed to be included in the third wiring layer (uppermost wiring layer).

Abstract: A semiconductor memory device comprises a memory cell array including a plurality of memory cells arranged in an array and having a plurality of rows and a plurality of columns, a plurality of column select gates, provided in association with the plurality of columns, for selecting at least one column of the plurality of columns of the memory cell array, a column decoder for outputting a column select signal to the plurality of column select gates, a plurality of sense amplifiers arranged between the memory cell array and the plurality of column select gates and provided in association with the plurality of columns, and a sense amplifier control circuit for controlling activation of the sense amplifiers independently such that the sense amplifier control circuit activates at least one selected sense amplifier of the plurality of sense amplifiers, which is associated with the at least one column of the plurality of columns selected by the plurality of column select gates, and maintains the unselected sense amp

Abstract: Even-numbered columns are arranged in the first memory cell array (bank), and odd-numbered columns are arranged in the second memory cell array (bank). A column address signal is input to an adder through a buffer. When data is read out of two or more columns, the adder generates a column address signal whose address value is more than that of the column address signal by one. The adder supplies a first column decoder with a column address signal for addressing an even-numbered column and supplies a second column decoder with a column address signal for addressing an odd-numbered column. Since the even-numbered columns and odd-numbered columns are arranged in their separate memory cell arrays, data read out of continuous two or more columns do not collide with each other.

Abstract: A semiconductor memory device includes a memory cell array, row decoder, bit line pairs, sense amplifier, sense amplifier control circuit, data latch, transfer gate, transfer gate control circuit, and write circuit. The memory cell array has dynamic memory cells arranged in an array form. The row decoder decodes a row address signal to select a desired one of rows of the memory cell array. Each of the bit line pairs is connected to those of the memory cells which are arranged on a corresponding one of columns of the memory cell array. The sense amplifier amplifies data read out on the paired bit lines and positively feeding data back to the paired bit lines to hold the data. The sense amplifier control circuit controls the operation of the sense amplifier. The data latch latches readout data and write data. The transfer gate transfers data between the data latch and the sense amplifier. The transfer gate control circuit controls the transfer gate.

Abstract: A semiconductor memory device includes a memory cell array, row decoder, bit line pairs, sense amplifier, sense amplifier control circuit, data latch, transfer gate, transfer gate control circuit, and write circuit. The memory cell array has dynamic memory cells arranged in an array form. The row decoder decodes a row address signal to select a desired one of rows of the memory cell array. Each of the bit line pairs is connected to those of the memory cells which are arranged on a corresponding one of columns of the memory cell array. The sense amplifier amplifies data read out on the paired bit lines and positively feeding data back to the paired bit lines to hold the data. The sense amplifier control circuit controls the operation of the sense amplifier. The data latch latches readout data and write data. The transfer gate transfers data between the data latch and the sense amplifier. The transfer gate control circuit controls the transfer gate.

Abstract: A semiconductor memory device comprises a plurality of memory cells including at least a first memory cell and a second memory cell, a first bit line connected to the first memory cell, a second bit line connected to the second memory cell and paired with the first bit line, an equalizer connected between the first and second bit lines, an amplifier connected between the first and second bit lines, a first driving signal line connected to the amplifier and drives the amplifier, a second driving signal line connected to the amplifier and paired with the first driving signal line, a driver for driving the amplifier and connected to the first and second driving signal lines and containing a precharger for presetting the potentials of the first and second driving signal lines to a predetermined precharge potential and a driving signal supply circuit for supplying a driving signal to the first and second driving signal lines, and a control circuit for controlling the equalizer and the driver, wherein the control c