Patents by Inventor Ryohei Higuchi

Ryohei Higuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170050359
    Abstract: An injection molding apparatus includes: an injection cylinder having a tip opening communicating with a cavity of a molding die; a resin supply portion configured to supply thermoplastic resin to a space in the injection cylinder; a reinforced fiber supply portion configured to supply fiber reinforced aggregates to the space in the injection cylinder; and a screw rotatably disposed in the injection cylinder, the screw being configured to compress and knead the thermoplastic resin in the injection cylinder and defibrate the fiber reinforced aggregates so as to disperse the fiber reinforced aggregates in the thermoplastic resin. The resin supply portion and the reinforced fiber supply portion are provided as different bodies. The reinforced fiber supply portion is placed on a tip opening side relative to the resin supply portion. The screw has a uniform groove depth.
    Type: Application
    Filed: August 10, 2016
    Publication date: February 23, 2017
    Applicants: AISIN SEIKI KABUSHIKI KAISHA, THE DOSHISHA, TOYO MACHINERY & METAL CO., LTD.
    Inventors: Ryohei HIGUCHI, Akira Inoue, Sou Shimokusuzono, Tatsuya Tanaka, Akimitsu Iwasaki
  • Publication number: 20140065257
    Abstract: An injection molding apparatus includes a heating device heating reinforcing fiber assemblies, an injection cylinder to which a thermoplastic resin and the reinforcing fiber assemblies are supplied, a first screw compressing and kneading the thermoplastic resin, a second screw fibrillating the reinforcing fiber assemblies and dispersing reinforcing fibers obtained by the fibrillation into the thermoplastic resin, a resin supply portion supplying the thermoplastic resin to a void formed between the injection cylinder and the first screw, and a reinforcing fiber supply portion supplying the reinforcing fiber assemblies to a void formed between the injection cylinder and the second screw. The second screw serves as one of a non-compression screw and a low compression screw including a low compression ratio by which the reinforcing fibers are inhibited from being excessively broken at a time of receiving a shearing force generated by a rotation of the second screw.
    Type: Application
    Filed: September 3, 2013
    Publication date: March 6, 2014
    Applicant: Aisin Seiki Kabushiki Kaisha
    Inventors: Shogo IZAWA, Hiroki Hara, Ryohei Higuchi
  • Patent number: 8244929
    Abstract: A data processing apparatus reduces the number of the buffer SRAMs to decrease chip area. The data processing apparatus includes an SDRAM address allocation register that holds information indicating which region of the SDRAM will be allocated to each of the IPs, and a buffer SRAM address allocation register that holds information indicating which region of the first and second buffer SRAMs will be allocated to each of the IPs. The bus I/F stores the data read from the SDRAM into the second buffer SRAM with reference to the SDRAM address allocation register and the buffer SRAM address allocation register. Therefore, it is not necessary to provide each of the IPs with a buffer SRAM, which allows integration into a small number of buffer SRAMs.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: August 14, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Ryohei Higuchi
  • Publication number: 20120089771
    Abstract: A data processing apparatus reduces the number of the buffer SRAMs to decrease chip area. The data processing apparatus includes an SDRAM address allocation register that holds information indicating which region of the SDRAM will be allocated to each of the IPs, and a buffer SRAM address allocation register that holds information indicating which region of the first and second buffer SRAMs will be allocated to each of the IPs. The bus I/F stores the data read from the SDRAM into the second buffer SRAM with reference to the SDRAM address allocation register and the buffer SRAM address allocation register. Therefore, it is not necessary to provide each of the IPs with a buffer SRAM, which allows integration into a small number of buffer SRAMs.
    Type: Application
    Filed: December 16, 2011
    Publication date: April 12, 2012
    Applicant: Renesas Electronics Corporation
    Inventor: Ryohei Higuchi
  • Patent number: 8145815
    Abstract: In a hierarchical bus structure employing a fixed-priority bus access arbitration scheme, accurate arbitration of bus access requests can be carried out even in situations where priority levels are updated according to a system operation mode. In each of a plurality of superordinate hierarchical bus circuits, access requests from respective bus masters included in each corresponding bus master group are arbitrated according to priority levels assigned thereto, and based on the result of the arbitration, a priority communication signal PRA/PRB indicating a priority level of each access-request-permitted bus master is fed to a subordinate bus controller. In a subordinate hierarchical bus circuit, under control of the subordinate bus controller, access request arbitration is carried out according to the priority communication signal PRA/PRB to select a superordinate hierarchical bus circuit or bus master having the highest priority level.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: March 27, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Ryohei Higuchi
  • Patent number: 8099530
    Abstract: A data processing apparatus reduces the number of the buffer SRAMs to decrease chip area. The data processing apparatus includes an SDRAM address allocation register that holds information indicating which region of the SDRAM will be allocated to each of the IPs, and a buffer SRAM address allocation register that holds information indicating which region of the first and second buffer SRAMs will be allocated to each of the IPs. The bus I/F stores the data read from the SDRAM into the second buffer SRAM with reference to the SDRAM address allocation register and the buffer SRAM address allocation register. Therefore, it is not necessary to provide each of the IPs with a buffer SRAM, which allows integration into a small number of buffer SRAMs.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: January 17, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Ryohei Higuchi
  • Publication number: 20100312935
    Abstract: In a hierarchical bus structure employing a fixed-priority bus access arbitration scheme, accurate arbitration of bus access requests can be carried out even in situations where priority levels are updated according to a system operation mode. In each of a plurality of superordinate hierarchical bus circuits, access requests from respective bus masters included in each corresponding bus master group are arbitrated according to priority levels assigned thereto, and based on the result of the arbitration, a priority communication signal PRA/PRB indicating a priority level of each access-request-permitted bus master is fed to a subordinate bus controller. In a subordinate hierarchical bus circuit, under control of the subordinate bus controller, access request arbitration is carried out according to the priority communication signal PRA/PRB to select a superordinate hierarchical bus circuit or bus master having the highest priority level.
    Type: Application
    Filed: May 5, 2010
    Publication date: December 9, 2010
    Inventor: Ryohei HIGUCHI
  • Publication number: 20100211704
    Abstract: A data processing apparatus reduces the number of the buffer SRAMs to decrease chip area. The data processing apparatus includes an SDRAM address allocation register that holds information indicating which region of the SDRAM will be allocated to each of the IPs, and a buffer SRAM address allocation register that holds information indicating which region of the first and second buffer SRAMs will be allocated to each of the IPs. The bus I/F stores the data read from the SDRAM into the second buffer SRAM with reference to the SDRAM address allocation register and the buffer SRAM address allocation register. Therefore, it is not necessary to provide each of the IPs with a buffer SRAM, which allows integration into a small number of buffer SRAMs.
    Type: Application
    Filed: February 12, 2010
    Publication date: August 19, 2010
    Applicant: Renesas Technology Corp.
    Inventor: Ryohei Higuchi
  • Publication number: 20080276021
    Abstract: A data transfer control apparatus has a plurality of bus slaves connected to a bus master via a bus interface unit for RAM connected to the bus master via a master bus, and a transfer bus which connects the first bus slave and plural second bus slaves in the plurality of bus slaves. When an instruction to execute data transfer via the transfer bus is given by a transfer instruction signal, data transfer between one second bus slave selected from the plural second bus slaves and the first bus slave via the transfer bus is carried out in response to a control signal contained in a control signal bus on a slave bus for RAM.
    Type: Application
    Filed: June 3, 2008
    Publication date: November 6, 2008
    Applicant: Renesas Technology Corp.
    Inventors: Ryohei Higuchi, Toshiyuki Hiraki
  • Patent number: 7395364
    Abstract: A data transfer control apparatus has a plurality of bus slaves connected to a bus master via a bus interface unit for RAM connected to the bus master via a master bus, and a transfer bus which connects the first bus slave and plural second bus slaves in the plurality of bus slaves. When an instruction to execute data transfer via the transfer bus is given by a transfer instruction signal, data transfer between one second bus slave selected from the plural second bus slaves and the first bus slave via the transfer bus is carried out in response to a control signal contained in a control signal bus on a slave bus for RAM.
    Type: Grant
    Filed: May 18, 2007
    Date of Patent: July 1, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Ryohei Higuchi, Toshiyuki Hiraki
  • Publication number: 20080126643
    Abstract: The invention provides a technique capable of allowing a CPU to execute interruption processing early. One of plural bus masters is a CPU. Each of the bus masters accesses a bus slave via a common bus. A bus access arbitration circuit arbitrates bus access requests among the bus masters. An interruption controller accepts an interruption request, and then notifies the CPU to execute interruption processing and outputs, to the bus access arbitration circuit, a preferential processing request signal for requesting preferential acceptance of the bus access request from the CPU. The bus access arbitration circuit receives the preferential processing request signal, and then accepts the bus access request from the CPU preferentially rather than the bus access requests from the bus masters other than the CPU.
    Type: Application
    Filed: November 15, 2007
    Publication date: May 29, 2008
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventor: Ryohei HIGUCHI
  • Publication number: 20070226391
    Abstract: A data transfer control apparatus has a plurality of bus slaves connected to a bus master via a bus interface unit for RAM connected to the bus master via a master bus, and a transfer bus which connects the first bus slave and plural second bus slaves in the plurality of bus slaves. When an instruction to execute data transfer via the transfer bus is given by a transfer instruction signal, data transfer between one second bus slave selected from the plural second bus slaves and the first bus slave via the transfer bus is carried out in response to a control signal contained in a control signal bus on a slave bus for RAM.
    Type: Application
    Filed: May 18, 2007
    Publication date: September 27, 2007
    Inventors: Ryohei Higuchi, Toshiyuki Hiraki
  • Patent number: 7240138
    Abstract: A data transfer control apparatus has a plurality of bus slaves connected to a bus master via a bus interface unit for RAM connected to the bus master via a master bus, and a transfer bus which connects the first bus slave and plural second bus slaves in the plurality of bus slaves. When an instruction to execute data transfer via the transfer bus is given by a transfer instruction signal, data transfer between one second bus slave selected from the plural second bus slaves and the first bus slave via the transfer bus is carried out in response to a control signal contained in a control signal bus on a slave bus for RAM.
    Type: Grant
    Filed: October 22, 2003
    Date of Patent: July 3, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Ryohei Higuchi, Toshiyuki Hiraki
  • Patent number: 7017000
    Abstract: Two bus masters share an external device. One particular bus master has an arrangement for issuing a data pre-read instruction, at the time of issuing a data read request. Upon reception of the data read request accompanying with the data pre-read instruction issued by the particular bus master, an external device controller instructs an external address generator to continuously generate an address for performing normal readout this time, and an address for the next pre-read, and executes readout by the next pre-read address, provided that when the normal readout this time is finished, the bus master has not issued a data read request. The normal data read based on the normal readout address this time is held in a data holder, and the pre-read data read based on the next pre-read address is stored in a pre-read data storage.
    Type: Grant
    Filed: October 7, 2003
    Date of Patent: March 21, 2006
    Assignee: Renesas Technology Corp.
    Inventor: Ryohei Higuchi
  • Patent number: 6948046
    Abstract: An SDRAM access control section activates a row of an SDRAM when a request is made to access the row in the continuous access mode. The SDRAM access control section outputs a read command or a write command to the SDRAM 300 when a request is made to access the SDRAM 300, without deactivating the accessed row, until a detection signal that detects the last column is asserted. The SDRAM access control section deactivates the accessed row when the detection signal is asserted.
    Type: Grant
    Filed: December 12, 2002
    Date of Patent: September 20, 2005
    Assignee: Renesas Technology Corp.
    Inventor: Ryohei Higuchi
  • Publication number: 20040205277
    Abstract: Two bus masters share an external device. One particular bus master has an arrangement for issuing a data pre-read instruction, at the time of issuing a data read request. Upon reception of the data read request accompanying with the data pre-read instruction issued by the particular bus master, an external device controller instructs an external address generator to continuously generate an address for performing normal readout this time, and an address for the next pre-read, and executes readout by the next pre-read address, provided that when the normal readout this time is finished, the bus master has not issued a data read request. The normal data read based on the normal readout address this time is held in a data holder, and the pre-read data read based on the next pre-read address is stored in a pre-read data storage.
    Type: Application
    Filed: October 7, 2003
    Publication date: October 14, 2004
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventor: Ryohei Higuchi
  • Publication number: 20040205278
    Abstract: A data transfer control apparatus has a plurality of bus slaves connected to a bus master via a bus interface unit for RAM connected to the bus master via a master bus, and a transfer bus which connects the first bus slave and plural second bus slaves in the plurality of bus slaves. When an instruction to execute data transfer via the transfer bus is given by a transfer instruction signal, data transfer between one second bus slave selected from the plural second bus slaves and the first bus slave via the transfer bus is carried out in response to a control signal contained in a control signal bus on a slave bus for RAM.
    Type: Application
    Filed: October 22, 2003
    Publication date: October 14, 2004
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Ryohei Higuchi, Toshiyuki Hiraki
  • Patent number: 6735639
    Abstract: DMA transfer request signals corresponding to respective channels are received and held in respective transfer request holding circuits. DMA transfers are assigned to the DMA transfer request signals respectively in a channel transfer request arbitrating circuit according to priorities set in advance for the DMA transfer request signals, and the DMA transfers for the DMA transfer request signals are performed in the order of lower priority. Also, a transfer waiting time period from the reception of one DMA transfer request signal to the assignment of the DMA transfer is measured in a transfer waiting time counter for each DMA transfer request signal, and the transfer waiting times are, for example, stored in a storing circuit and are selectively read out.
    Type: Grant
    Filed: May 6, 2002
    Date of Patent: May 11, 2004
    Assignee: Renesas Technology Corp.
    Inventor: Ryohei Higuchi
  • Publication number: 20030229750
    Abstract: An SDRAM access control section activates a row of an SDRAM when a request is made to access the row in the continuous access mode. The SDRAM access control section outputs a read command or a write command to the SDRAM 300 when a request is made to access the SDRAM 300, without deactivating the accessed row, until a detection signal that detects the last column is asserted. The SDRAM access control section deactivates the accessed row when the detection signal is asserted.
    Type: Application
    Filed: December 12, 2002
    Publication date: December 11, 2003
    Inventor: Ryohei Higuchi
  • Publication number: 20030088718
    Abstract: A plurality of DMA transfer request signals corresponding to a plurality of channels are received and held in a plurality of transfer request holding circuits respectively. A plurality of DMA transfers are assigned to the DMA transfer request signals respectively in a channel transfer request arbitrating circuit according to priorities set in advance for the DMA transfer request signals, and the DMA transfers for the DMA transfer request signals are performed in the order of lowering the priority. Also, a transfer waiting time period from the reception of one DMA transfer request signal to the assignment of the DMA transfer is measured in a transfer waiting time counter for each DMA transfer request signal, and the transfer waiting times are, for example, stored in a storing circuit and are selectively read out.
    Type: Application
    Filed: May 6, 2002
    Publication date: May 8, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Ryohei Higuchi