Abstract: In a memory device, row and column decoders are connected through a common address signal line to an address buffer, and the row decoder is connected through a switch to the common address signal line. When the address buffer delivers a first address signal, the switch is turned on so that the first address signal is applied to both of the column and row decoders. The column decoder includes therein provision for disabling the column decoder when the first address signal is applied to column decoder. The column decoder therefore does not respond to the first address signal. Subsequently, when the address buffer delivers a second address signal, the switch is turned off so that the row decoder is not applied with the second address signal but the column decoder responds to the second address signal. Thus, the row and column address respond to the first and second address signals respectively.

Abstract: PCT No. PCT/JP78/00013 Sec. 371 Date June 28, 1979 Sec. 102(e) Date June 19, 1979 PCT Filed Oct. 26, 1978 PCT Pub. No. W079/00240 PCT Pub. Date May 3, 1979It has previously been known that the poor pigment dispersibility of an acrylic paint is its defect. The present invention provides a modified acrylic copolymer having superior pigment dispersibility and being suitable as a vehicle for acrylic paints. The copolymer is obtained by polymerizing specified proportions of a polyester containing an unsaturated double bond, a dialkylaminoalkyl (meth)acrylate, methyl methacrylate and another polymerizable monomer, and has a weight average molecular weight/number average molecular weight ratio within the range of 3 to 20.

Abstract: A first semiconductor circuit element including a first electrode is formed on a semiconductor substrate, an inter-layer insulating layer for insulating the first electrode is formed on the first electrode, and a first penetrating opening is provided in a part of the inter-layer insulating layer.Subsequently, a step of forming a second semiconductor circuit element is carried out, this step including a step of forming a second electrode so that at least a part thereof may overlie the inter-layer insulating layer at an area other than the first penetrating opening. Further, a subsidiary interconnection conductive layer is buried into the first opening. Another insulating layer is formed on the structure thus formed, whereupon second and third penetrating openings are respectively provided in the insulating layer over the second electrode and the interconnection subsidiary conductive layer.First and second interconnection conductors are respectively buried into the second and third penetrating openings.

Abstract: In a memory system where certain memory systems a signal detector is provided which begins to detect the voltage of a data line to which a plurality of memory cells are connected when the voltage of a latch node of the detector is shifted from a first to a second level by discharging the node through a switch in response to an input signal provided by a pulse circuit. To avoid discharging the node at an improper time, a signal transformation circuit is interposed between the pulse circuit and the switch to provide the switch with a signal to turn it on only when the level of the signal provided by the pulse circuit is high enough. In this manner, improper discharging due to shifts in the pulse circuit can be avoided.

Abstract: A MOS type field effect transistor has an electrode, which is in the neighborhood of, but not in contact with, the drain diffusion region and is electrically connected with the surface portion of the semiconductor substrate in which the MOS type field effect transistor is formed, and whose potential is held at the rear surface potential of the semiconductor substrate, i. e., the substrate bias potential.

Abstract: A protective circuit comprises a metal-oxide-semiconductor field effect transistor (MOSFET) to be protected, and a depletion-type MOSFET the gate and source of which are connected to each other and the souce of which is connected to the gate of the MOSFET to be protected, whereby the protective circuit which is suitable for a high-speed operation is completed.