Patents by Inventor Ryoichi Kajiwara

Ryoichi Kajiwara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9736952
    Abstract: There is provided an on-vehicle electronic module that includes an external connecting function and environment resistant reliability similar to a previous on-vehicle electronic module and that simultaneously achieves downsizing without a male connector housing component and cost reduction due to reduction of the number of components and assembly man-hours. There are included a circuit board 1 including a mounting region 2 and a terminal forming region 3, and a case housing the mounting region 2 of the circuit board 1. Electronic components 9 and 10 are mounted on the mounting region 2. A board terminal is formed in the terminal forming region 3. The case includes a case member 13 integrally formed with a wall surface and a male connector housing 13a. The wall surface forms a case internal space 21 that houses the mounting region 2. A female connector is mounted to the male connector housing 13a.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: August 15, 2017
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Ryoichi Kajiwara, Toshiaki Ishii, Masaru Kamoshida
  • Publication number: 20160010213
    Abstract: Provided are a metal-resin composite having excellent adhesive strength, a method for producing the same, a busbar, a module case, and a resinous connector part. The metal-resin composite comprises a metallic member 1 including a metal with a high melting point of 500° C. or more, a resin member 2 being integrated with the metallic member 1; and an alloy layer 3 including a metal with a low melting point lower than 500° C. The alloy layer 3 is arranged between the metallic member 1 and the resin member 2, and has average surface roughness thereof in the range from 5 nm or more to less than 1 ?m at the interface between the alloy layer 3 and the resin member 2. Herein, a period of the unevenness formed on the interface of the alloy layer 3 is in the range from 5 nm or more to less than 1 ?m.
    Type: Application
    Filed: September 18, 2015
    Publication date: January 14, 2016
    Applicant: HITACHI, LTD.
    Inventors: Ryoichi Kajiwara, Shigehisa Motowaki, Yusuke Asaumi
  • Publication number: 20150366086
    Abstract: There is provided an on-vehicle electronic module that includes an external connecting function and environment resistant reliability similar to a previous on-vehicle electronic module and that simultaneously achieves downsizing without a male connector housing component and cost reduction due to reduction of the number of components and assembly man-hours. There are included a circuit board 1 including a mounting region 2 and a terminal forming region 3, and a case housing the mounting region 2 of the circuit board 1. Electronic components 9 and 10 are mounted on the mounting region 2. A board terminal is formed in the terminal forming region 3. The case includes a case member 13 integrally formed with a wall surface and a male connector housing 13a. The wall surface forms a case internal space 21 that houses the mounting region 2. A female connector is mounted to the male connector housing 13a.
    Type: Application
    Filed: January 17, 2014
    Publication date: December 17, 2015
    Inventors: Ryoichi KAJIWARA, Toshiaki ISHII, Masaru KAMOSHIDA
  • Patent number: 9209044
    Abstract: Provided are a metal-resin composite having excellent adhesive strength, a method for producing the same, a busbar, a module case, and a resinous connector part. The metal-resin composite comprises a metallic member 1 including a metal with a high melting point of 500° C. or more, a resin member 2 being integrated with the metallic member 1; and an alloy layer 3 including a metal with a low melting point lower than 500° C. The alloy layer 3 is arranged between the metallic member 1 and the resin member 2, and has average surface roughness thereof in the range from 5 nm or more to less than 1 ?m at the interface between the alloy layer 3 and the resin member 2. Herein, a period of the unevenness formed on the interface of the alloy layer 3 is in the range from 5 nm or more to less than 1 ?m.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: December 8, 2015
    Assignee: HITACHI, LTD.
    Inventors: Ryoichi Kajiwara, Shigehisa Motowaki, Yusuke Asaumi
  • Patent number: 9177833
    Abstract: Conventional surface roughening plating technology cannot always improve the adhesion between a leadframe and a plating film and it depends on the material used for surface roughening plating. Conventional surface roughening technology by etching can only be used for leadframes made of limited materials. Improved adhesion cannot therefore be achieved between a metal member such as leadframe and a sealing resin. A manufacturing method of a semiconductor device according to one embodiment is to carry out resin sealing using a metal member such as leadframe which has been subjected to alloying treatment of a base material and Zn plated on the surface thereof.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: November 3, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Takuya Nakajo, Masaki Tamura, Yasushi Takahashi, Keiichi Okawa, Ryoichi Kajiwara, Sigehisa Motowaki, Hiroshi Hozouji
  • Patent number: 8975747
    Abstract: There is provided a wiring material including a core layer made of metal and a clad layer made of metal and a fiber in which the core layer is copper or an alloy containing copper and the clad layer is formed of copper or the alloy containing copper and the fiber having a thermal expansion coefficient lower than that of copper, the wiring material having a stacked structure in which at least one surface of the core layer is closely adhered to the clad layer, and the fiber in the clad layer is arranged so as to be parallel to the surface of the core layer.
    Type: Grant
    Filed: August 13, 2012
    Date of Patent: March 10, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Ando, Ryoichi Kajiwara, Hiroshi Hozoji
  • Publication number: 20140264383
    Abstract: A semiconductor device includes a die pad, an SiC chip mounted on the die pad, a porous first sintered Ag layer bonding the die pad and the SiC chip, and a reinforcing resin portion covering a surface of the first sintered Ag layer and formed in a fillet shape. The semiconductor device further includes a source lead electrically connected to a source electrode of the SiC chip, a gate lead electrically connected to a gate electrode, a drain lead electrically connected to a drain electrode, and a sealing body which covers the SiC chip, the first sintered Ag layer, and a part of the die pad, and the reinforcing resin portion covers a part of a side surface of the SiC chip.
    Type: Application
    Filed: March 14, 2014
    Publication date: September 18, 2014
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Ryoichi KAJIWARA, Takuya NAKAJO, Katsuo ARAI, Yuichi YATO, Hiroi OKA, Hiroshi HOZOJI
  • Patent number: 8816411
    Abstract: A semiconductor device featuring a semiconductor chip including a MOSFET and having a first main surface and a second, opposing main surface, a source electrode pad and a gate electrode pad over the first main surface, a drain electrode over the second main surface, a source external terminal and a gate external terminal, each having a first main surface electrically connected to the source electrode pad and gate electrode pad of the chip, respectively, and a drain external terminal having a first main surface and a second, opposing main surface and being electrically connected to the second main surface of the chip, each of the source, gate and drain external terminals having second main surfaces thereof in a same plane, and, in a plan view of the external terminals, the gate external terminal has a portion located between the source and drain external terminals in at least one direction.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: August 26, 2014
    Assignees: Renesas Electronics Corporation, Renesas Eastern Japan Semiconductor, Inc.
    Inventors: Ryoichi Kajiwara, Masahiro Koizumi, Toshiak Morita, Kazuya Takahashi, Munehisa Kishimoto, Shigeru Ishii, Toshinori Hirashima, Yasushi Takahashi, Toshiyuki Hata, Hiroshi Sato, Keiichi Ookawa
  • Publication number: 20140191399
    Abstract: There is provided a wiring material including a core layer made of metal and a clad layer made of metal and a fiber in which the core layer is copper or an alloy containing copper and the clad layer is formed of copper or the alloy containing copper and the fiber having a thermal expansion coefficient lower than that of copper, the wiring material having a stacked structure in which at least one surface of the core layer is closely adhered to the clad layer, and the fiber in the clad layer is arranged so as to be parallel to the surface of the core layer.
    Type: Application
    Filed: August 13, 2012
    Publication date: July 10, 2014
    Inventors: Takashi Ando, Ryoichi Kajiwara, Hiroshi Hozoji
  • Patent number: 8643185
    Abstract: A die bonding portion is metallically bonded by well-conductive Cu metal powders with a maximum particle diameter of about 15 ?m to 200 ?m and adhesive layers of Ag, and minute holes are evenly dispersed in a joint layer. With this structure, the reflow resistance of about 260° C. and reliability under thermal cycle test can be ensured without using lead.
    Type: Grant
    Filed: October 7, 2008
    Date of Patent: February 4, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Ryoichi Kajiwara, Kazutoshi Itou, Hiroi Oka, Takuya Nakajo, Yuichi Yato
  • Patent number: 8629352
    Abstract: There is provided an enameled insulated wire, which includes: a metal conductor; an intermediate layer around the metal conductor, the intermediate layer containing metal oxide particles, the metal oxide particles including at least one oxide selected from a group consisting of zinc oxides, tin oxides, compound oxides of zinc and the metal constituent of the metal conductor, and compound oxides of tin and the metal constituent of the metal conductor, diameter of the metal oxide particles being predominantly from 1 to 50 nm; and an insulation coating around the intermediate layer.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: January 14, 2014
    Assignees: Hitachi Cable, Ltd., Hitachi, Ltd.
    Inventors: Yoshiyuki Ando, Tomiya Abe, Shigehisa Motowaki, Ryoichi Kajiwara
  • Publication number: 20130264696
    Abstract: A semiconductor device featuring a semiconductor chip including a MOSFET and having a first main surface and a second, opposing main surface, a source electrode pad and a gate electrode pad over the first main surface, a drain electrode over the second main surface, a source external terminal and a gate external terminal, each having a first main surface electrically connected to the source electrode pad and gate electrode pad of the chip, respectively, and a drain external terminal having a first main surface and a second, opposing main surface and being electrically connected to the second main surface of the chip, each of the source, gate and drain external terminals having second main surfaces thereof in a same plane, and, in a plan view of the external terminals, the gate external terminal has a portion located between the source and drain external terminals in at least one direction.
    Type: Application
    Filed: May 31, 2013
    Publication date: October 10, 2013
    Inventors: Ryoichi KAJIWARA, Masahiro KOIZUMI, Toshiaki MORITA, Kazuya TAKAHASHI, Munehisa KISHIMOTO, Shigeru ISHII, Toshinori HIRASHIMA, Yasushi TAKAHASHI, Toshiyuki HATA, Hiroshi SATO, Keiichi OOKAWA
  • Publication number: 20130228907
    Abstract: Conventional surface roughening plating technology cannot always improve the adhesion between a leadframe and a plating film and it depends on the material used for surface roughening plating. Conventional surface roughening technology by etching can only be used for leadframes made of limited materials. Improved adhesion cannot therefore be achieved between a metal member such as leadframe and a sealing resin. A manufacturing method of a semiconductor device according to one embodiment is to carry out resin sealing using a metal member such as leadframe which has been subjected to alloying treatment of a base material and Zn plated on the surface thereof.
    Type: Application
    Filed: February 15, 2013
    Publication date: September 5, 2013
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Takuya NAKAJO, Masaki TAMURA, Yasushi TAKAHASHI, Keiichi OKAWA, Ryoichi KAJIWARA, Sigehisa MOTOWAKI, Hiroshi HOZOUJI
  • Patent number: 8492202
    Abstract: In a structure of a semiconductor device, a Si chip and a metal leadframe are jointed by metallic bond via a porous joint layer made of high conductive metal, having a three-dimensional network structure and using Ag as a bonding material, and a film containing Zn oxide or Al oxide is formed on a surface of a semiconductor assembly contacting to a polymer resin. In this manner, by the joint with the joint layer having the porous structure mainly made of Ag, thermal stress load of the Si chip can be reduced, and fatigue life of the joint layer itself can be improved. Besides, since adhesion of the polymer resin to the film can be enhanced by the anchor effect, occurrence of cracks in a bonding portion can be prevented, so that a highly-reliable Pb-free semiconductor device can be provided.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: July 23, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Ryoichi Kajiwara, Shigehisa Motowaki, Kazutoshi Ito, Toshiaki Ishii, Katsuo Arai, Takuya Nakajo, Hidemasa Kagii
  • Patent number: 8455986
    Abstract: A semiconductor device featuring a semiconductor chip having a first main surface and a second, opposing main surface and including a MOSFET having source and gate electrodes formed on the first main surface and a drain electrode thereof formed on the second main surface, first and second conductive members acting as lead terminals for the source and gate electrodes, respectively, are disposed over the first main surface, each of the first and second conductive members has a part overlapped with the chip in a plan view, a sealing body sealing the chip and parts of the first and second conductive members such that a part of the first conductive member is projected outwardly from a first side surface of the sealing body and parts of the first and second conductive members are projected outwardly from the opposing second side surface of the sealing body in a plan view.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: June 4, 2013
    Assignees: Renesas Electronics Corporation, Hitachi Tohbu Semiconductor, Ltd.
    Inventors: Ryoichi Kajiwara, Masahiro Koizumi, Toshiaki Morita, Kazuya Takahashi, Munehisa Kishimoto, Shigeru Ishii, Toshinori Hirashima, Yasushi Takahashi, Toshiyuki Hata, Hiroshi Sato, Keiichi Ookawa
  • Patent number: 8313983
    Abstract: A fabrication method for a resin encapsulated semiconductor device includes the steps of: (1) die-bonding a semiconductor device to a first electrical connection metallic terminal of a wiring substrate; (2) electrically connecting an electrode of the semiconductor device and a second electrical connection metallic terminal of the wiring substrate via an electrical connector; (3) surface treating such an assembly by applying a solution to a surface of the assembly and baking the applied solution; and (4) transfer-molding an insulating encapsulating resin onto the surface-treated assembly.
    Type: Grant
    Filed: May 16, 2011
    Date of Patent: November 20, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Ryoichi Kajiwara, Shigehisa Motowaki, Kazutoshi Itou, Hiroshi Hozoji
  • Patent number: 8314484
    Abstract: In a structure of a semiconductor device, a Si chip and a metal leadframe are jointed by metallic bond via a porous joint layer made of high conductive metal, having a three-dimensional network structure and using Ag as a bonding material, and a film containing Zn oxide or Al oxide is formed on a surface of a semiconductor assembly contacting to a polymer resin. In this manner, by the joint with the joint layer having the porous structure mainly made of Ag, thermal stress load of the Si chip can be reduced, and fatigue life of the joint layer itself can be improved. Besides, since adhesion of the polymer resin to the film can be enhanced by the anchor effect, occurrence of cracks in a bonding portion can be prevented, so that a highly-reliable Pb-free semiconductor device can be provided.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: November 20, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Ryoichi Kajiwara, Shigehisa Motowaki, Kazutoshi Ito, Toshiaki Ishii, Katsuo Arai, Takuya Nakajo, Hidemasa Kagii
  • Patent number: 8303854
    Abstract: An object of the present invention is to provide a composition of a sintering Ag paste which can metallically bond to a nonprecious metal member with high strength as well as to a precious metal member, in a sintering Ag paste which metallically bonds to a metal at a low temperature, and to provide a bonding method to obtain a joint part having high strength. The sintering Ag paste is a material containing a solution of an organic silver complex that is easily decomposed by heat regardless of an atmosphere. Furthermore, the bonding method includes: metallizing a face of a nonprecious metal with Ag in a non-oxidizing atmosphere in a step prior to sintering Ag particles; and then sintering the Ag particles in an oxidizing atmosphere.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: November 6, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Ryoichi Kajiwara, Shigehisa Motowaki, Yusuke Asaumi
  • Publication number: 20120217556
    Abstract: A semiconductor device featuring a semiconductor chip having a first main surface and a second, opposing main surface and including a MOSFET having source and gate electrodes formed on the first main surface and a drain electrode thereof formed on the second main surface, first and second conductive members acting as lead terminals for the source and gate electrodes, respectively, are disposed over the first main surface, each of the first and second conductive members has a part overlapped with the chip in a plan view, a sealing body sealing the chip and parts of the first and second conductive members such that a part of the first conductive member is projected outwardly from a first side surface of the sealing body and parts of the first and second conductive members are projected outwardly from the opposing second side surface of the sealing body in a plan view.
    Type: Application
    Filed: April 30, 2012
    Publication date: August 30, 2012
    Inventors: Ryoichi Kajiwara, Masahiro Koizumi, Toshiaki Morita, Kazuya Takahashi, Munehisa Kishimoto, Shigeru Ishii, Toshinori Hirashima, Yasushi Takahashi, Toshiyuki Hata, Hiroshi Sato, Keiichi Ookawa
  • Publication number: 20120141818
    Abstract: Provided are a metal-resin composite having excellent adhesive strength, a method for producing the same, a busbar, a module case, and a resinous connector part. The metal-resin composite comprises a metallic member 1 including a metal with a high melting point of 500° C. or more, a resin member 2 being integrated with the metallic member 1; and an alloy layer 3 including a metal with a low melting point lower than 500° C. The alloy layer 3 is arranged between the metallic member 1 and the resin member 2, and has average surface roughness thereof in the range from 5 nm or more to less than 1 ?m at the interface between the alloy layer 3 and the resin member 2. Herein, a period of the unevenness formed on the interface of the alloy layer 3 is in the range from 5 nm or more to less than 1 ?m.
    Type: Application
    Filed: December 1, 2011
    Publication date: June 7, 2012
    Inventors: Ryoichi KAJIWARA, Shigehisa Motowaki, Yusuke Asaumi