Patents by Inventor Ryoichi Kajiwara

Ryoichi Kajiwara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070125449
    Abstract: The present invention intends to provide a power semiconductor device using a high-temperature lead-free solder material, the high-temperature lead-free solder material having the heat resistant property at 280° C. or more, and the bondability at 400° C. or less, and excellent in the suppliabilty and wettability of solder, and in the high-temperature storage reliability and the temperature cycle reliability. In the power semiconductor device according to the present invention, a semiconductor element and a metal electrode member were bonded each other by a high-temperature solder material comprising Sn, Sb, Ag, and Cu as the main constitutive elements and the rest of other unavoidable impurity elements wherein the high-temperature solder material comprises 42 wt %?Sb/(Sn+Sb)?48 wt %, 5 wt %?Ag<20 wt %, 3 wt %?Cu<10 wt %, and Ag+Cu?25 wt %.
    Type: Application
    Filed: December 5, 2006
    Publication date: June 7, 2007
    Inventors: Ryoichi Kajiwara, Kazutoshi Itou
  • Publication number: 20070040250
    Abstract: A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal.
    Type: Application
    Filed: October 31, 2006
    Publication date: February 22, 2007
    Inventors: Ryoichi Kajiwara, Masahiro Koizumi, Toshiaki Morita, Kazuya Takahashi, Munehisa Kishimoto, Shigeru Ishii, Toshinori Hirashima, Yasushi Takahashi, Toshiyuki Hata, Hiroshi Sato, Keiichi Ookawa
  • Publication number: 20070040248
    Abstract: A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal.
    Type: Application
    Filed: October 31, 2006
    Publication date: February 22, 2007
    Inventors: Ryoichi Kajiwara, Masahiro Koizumi, Toshiaki Morita, Kazuya Takahashi, Munehisa Kishimoto, Shigeru Ishii, Toshinori Hirashima, Yasushi Takahashi, Toshiyuki Hata, Hiroshi Sato, Keiichi Ookawa
  • Publication number: 20070040249
    Abstract: A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal.
    Type: Application
    Filed: October 31, 2006
    Publication date: February 22, 2007
    Inventors: Ryoichi Kajiwara, Masahiro Koizumi, Toshiaki Morita, Kazuya Takahashi, Munehisa Kishimoto, Shigeru Ishii, Toshinori Hirashima, Yasushi Takahashi, Toshiyuki Hata, Hiroshi Sato, Keiichi Ookawa
  • Publication number: 20070029540
    Abstract: A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal.
    Type: Application
    Filed: October 5, 2006
    Publication date: February 8, 2007
    Inventors: Ryoichi Kajiwara, Masahiro Koizumi, Toshiaki Morita, Kazuya Takahashi, Munehisa Kishimoto, Shigeru Ishii, Toshinori Hirashima, Yasushi Takahashi, Toshiyuki Hata, Hiroshi Sato, Keiichi Ookawa
  • Publication number: 20060197196
    Abstract: A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal.
    Type: Application
    Filed: May 2, 2006
    Publication date: September 7, 2006
    Inventors: Ryoichi Kajiwara, Masahiro Koizumi, Toshiaki Morita, Kazuya Takahashi, Munehisa Kishimoto, Shigeru Ishii, Toshinori Hirashima, Yasushi Takahashi, Toshiyuki Hata, Hiroshi Sato, Keiichi Ookawa
  • Publication number: 20060197200
    Abstract: A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal.
    Type: Application
    Filed: May 2, 2006
    Publication date: September 7, 2006
    Inventors: Ryoichi Kajiwara, Masahiro Koizumi, Toshiaki Morita, Kazuya Takahashi, Munehisa Kishimoto, Shigeru Ishii, Toshinori Hirashima, Yasushi Takahashi, Toshiyuki Hata, Hiroshi Sato, Keiichi Ookawa
  • Publication number: 20040217474
    Abstract: A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal.
    Type: Application
    Filed: May 28, 2004
    Publication date: November 4, 2004
    Inventors: Ryoichi Kajiwara, Masahiro Koizumi, Toshiaki Morita, Kazuya Takahashi, Munehisa Kishimoto, Shigeru Ishii, Toshinori Hirashima, Toshiyuki Hata, Hiroshi Sato, Keiichi Ookawa
  • Patent number: 6798072
    Abstract: A semiconductor device includes a semiconductor chip and a printed circuit board. Metal electrodes of the semiconductor chip and the internal connection terminals of the printed circuit board are electrically connected through the metallic joining via precious metal bumps. A melting point of a metal material constituting each of the metallic joining parts is equal to or higher than 275 degrees, and a space defined between the chip and the board is filled with resin (under fill) containing 50 vol % or more inorganic fillers.
    Type: Grant
    Filed: February 27, 2001
    Date of Patent: September 28, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Ryoichi Kajiwara, Masahiro Koizumi, Toshiaki Morita, Kazuya Takahashi, Asao Nishimura, Masayoshi Shinoda
  • Patent number: 6784554
    Abstract: In a semiconductor device in which an LSI chip comprising electrodes with a 100 &mgr;m pitch or less and 50 or more pins is mounted directly on an organic substrate, a mounting structure and a manufacturing method thereof are provided excellent in the solder resistant reflow property, temperature cycle reliability and high temperature/high humidity reliability of the semiconductor device. Electrode Au bumps of the chip and an Au film at the uppermost surface of connection terminals of the substrate are directly flip-chip bonded by Au/Au metal bonding and the elongation of the bonded portion of the Au bump is 2 &mgr;m or more. The method of obtaining the bonded structure involves a process of supersonically bonding both of the bonding surfaces within 10 min after sputter cleaning, under the bonding conditions selected from room temperature on the side of the substrate, room temperature to 150° C.
    Type: Grant
    Filed: December 18, 2002
    Date of Patent: August 31, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Ryoichi Kajiwara, Masahiro Koizumi, Masayoshi Shinoda, Akihiko Narisawa, Asao Nishimura, Toshiaki Morita, Kazuya Takahashi, Kazutoshi Itou
  • Patent number: 6774466
    Abstract: A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal.
    Type: Grant
    Filed: January 28, 2000
    Date of Patent: August 10, 2004
    Assignees: Renesas Technology Corp., Hitachi Tohbu Semiconductor, Ltd.
    Inventors: Ryoichi Kajiwara, Masahiro Koizumi, Toshiaki Morita, Kazuya Takahashi, Munehisa Kishimoto, Shigeru Ishii, Toshinori Hirashima, Yasushi Takahashi, Toshiyuki Hata, Hiroshi Sato, Keiichi Ookawa
  • Publication number: 20040150082
    Abstract: A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal.
    Type: Application
    Filed: January 16, 2004
    Publication date: August 5, 2004
    Inventors: Ryoichi Kajiwara, Masahiro Koizumi, Toshiaki Morita, Kazuya Takahashi, Munehisa Kishimoto, Shigeru Ishii, Toshinori Hirashima, Yasushi Takahashi, Toshiyuki Hata, Hiroshi Sato, Keiichi Ookawa
  • Publication number: 20030127747
    Abstract: In a semiconductor device in which an LSI chip comprising electrodes with a 100 &mgr;m pitch or less and 50 or more pins is mounted directly on an organic substrate, a mounting structure and a manufacturing method thereof are provided excellent in the solder resistant reflow property, temperature cycle reliability and high temperature/high humidity reliability of the semiconductor device. Electrode Au bumps of the chip and an Au film at the uppermost surface of connection terminals of the substrate are directly flip-chip bonded by Au/Au metal bonding and the elongation of the bonded portion of the Au bump is 2 &mgr;m or more. The method of obtaining the bonded structure involves a process of supersonically bonding both of the bonding surfaces within 10 min after sputter cleaning, under the bonding conditions selected from room temperature on the side of the substrate, room temperature to 150° C.
    Type: Application
    Filed: December 18, 2002
    Publication date: July 10, 2003
    Inventors: Ryoichi Kajiwara, Masahiro Koizumi, Masayoshi Shinoda, Akihiko Narisawa, Asao Nishimura, Toshiaki Morita, Kazuya Takahashi, Kazutoshi Itou
  • Patent number: 6569764
    Abstract: The semiconductor device includes a semiconductor chip having a first electrode and a second electrode formed on a first main surface and a third electrode formed on a second main surface opposite the first main surface. A first portion of a first lead is placed on the first electrode and a second portion of the first lead is located outside the semiconductor chip. A first portion of a second lead is placed on the second electrode and a second portion of the second lead is located outside the semiconductor chip. A plurality of projecting electrodes are provided between the first portion of the first lead and the first electrode and between the first portion of the second lead and the second electrode to electrically connect them. An insulating sheet is provided between the first portion of the first lead and the first main surface of the semiconductor chip and between the first portion of the second lead and the first main surface of the semiconductor chip.
    Type: Grant
    Filed: August 29, 2000
    Date of Patent: May 27, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Toshinori Hirashima, Yasushi Takahashi, Ryoichi Kajiwara, Masahiro Koizumi, Munehisa Kishimoto
  • Publication number: 20030001286
    Abstract: A semiconductor chip and an organic substrate are bonded together in an atmosphere having a reduced moisture content through Au bumps which have been subjected to a cleaning treatment therebetween. Using this bonding technique, a semiconductor chip and an organic substrate can be bonded together in a sufficiently high strength with use of Au bumps having a diameter of not larger than 300 &mgr;m, a height of not smaller than 50 &mgr;m, and a height/diameter ratio of not lower than 1/5, thus indicating a reduced strain.
    Type: Application
    Filed: September 4, 2002
    Publication date: January 2, 2003
    Inventors: Ryoichi Kajiwara, Masahiro Koizumi, Toshiaki Morita, Kazuya Takahashi, Asao Nishimura, Kunihiro Tsubosaki
  • Publication number: 20020056906
    Abstract: A semiconductor device includes a semiconductor chip and a printed circuit board. Metal electrodes of the semiconductor chip and the internal connection terminals of the printed circuit board are electrically connected through the metallic joining via precious metal bumps. A melting point of a metal material constituting each of the metallic joining parts is equal to or higher than 275 degrees, and a space defined between the chip and the board is filled with resin (under fill) containing 50 vol % or more inorganic fillers.
    Type: Application
    Filed: February 27, 2001
    Publication date: May 16, 2002
    Inventors: Ryoichi Kajiwara, Masahiro Koizumi, Toshiaki Morita, Kazuya Takahashi, Asao Nishimura, Masayoshi Shinoda
  • Patent number: 5884835
    Abstract: In a case of ultrasonic bonding of a bonding wire to a metal pad provided on a semiconductor substrate, the vibration amplitude of a tip end of the bonding tool is set to be smaller than the film thickness of the metal pad, and the vibration frequency of the bonding tool is set to be higher than 70 kHz. According physical damage, such as cracks produced in a portion beneath the metal pad, can be prevented.
    Type: Grant
    Filed: July 26, 1996
    Date of Patent: March 23, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Ryoichi Kajiwara, Toshiyuki Takahashi, Kazuya Takahashi, Masahiro Koizumi, Hiroshi Watanabe, Yukiharu Akiyama
  • Patent number: 5431324
    Abstract: An ultrasonic bonding apparatus comprises an ultrasonic wave controller, a bonding system including a bonding head, a laser oscillator, a laser optics, a vibration monitoring system including a vibrometer, and a mechanism for feeding a result of monitoring back to a bonding condition.
    Type: Grant
    Filed: January 22, 1993
    Date of Patent: July 11, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Ryoichi Kajiwara, Mituo Katou, Kazuya Takahashi, Minoru Maruta, Tokiyuki Seto, Kunihiro Tsubosaki
  • Patent number: 5323952
    Abstract: A bonding apparatus comprising a bonding tool, means for driving the bonding tool, means for detecting an amount of crushing of a bonding portion during bonding, means for calculating a rate of change of the amount of crushing detected by the amount-of-crushing detecting means, means for setting a target value, which is inputted from an external source, of the amount of crushing of the bonding portion, and means for controlling the driving means. When the rate of change of the amount of crushing calculated by the calculating means is smaller than a predetermined value, the controlling means compares the amount of crushing detected by the amount-of-crushing detecting means with the target value. When the amount of crushing detected by the amount-of-crushing detecting means is smaller than the target value, the controlling means discriminates that the bonding is being performed in a satisfactory manner and hence should be continued.
    Type: Grant
    Filed: September 18, 1992
    Date of Patent: June 28, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Mituo Kato, Ryoichi Kajiwara, Kazuya Takahashi, Setuo Sekine, Tokiyuki Seto
  • Patent number: 4996589
    Abstract: A number of LSI chips (9) are mounted on a wiring substrate (12). A cooling element (68) comprises a housing (1), a bellows (2) and a cooling plate (6) for introducing a cooling medium. The cooling element is connected to the LSI chip by low melting solder, at the same time, the cooling plate is connected to the wiring substrate through a skirt (5) which is connected to the cooling plate and also connected to the wiring substrate by a low melting solder.
    Type: Grant
    Filed: October 17, 1988
    Date of Patent: February 26, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Ryoichi Kajiwara, Takao Funamoto, Mituo Kato, Hiroshi Wachi, Tomohiko Shida