Abstract: Crosstalk is suppressed in a wiring layer.

Abstract: A semiconductor device according to an embodiment of the present disclosure includes: a first substrate including a first junction portion; and a second substrate including a second junction portion. The second junction portion is joined to the first junction portion. The first substrate further includes a first multilayer wiring layer in which one surface of a first wiring line faces a first insulating layer and another surface opposed to the one surface is in contact with a second insulating layer. The first multilayer wiring layer is electrically coupled to the first junction portion via the first insulating layer. The first wiring line is formed closest to a junction surface with the second substrate. The second insulating layer has a lower relative dielectric constant than a relative dielectric constant of the first insulating layer.

Abstract: A semiconductor device according to an embodiment of the present disclosure includes: a first substrate including a first junction portion; and a second substrate including a second junction portion. The second junction portion is joined to the first junction portion. The first substrate further includes a first multilayer wiring layer in which one surface of a first wiring line faces a first insulating layer and another surface opposed to the one surface is in contact with a second insulating layer. The first multilayer wiring layer is electrically coupled to the first junction portion via the first insulating layer. The first wiring line is formed closest to a junction surface with the second substrate. The second insulating layer has a lower relative dielectric constant than a relative dielectric constant of the first insulating layer.

Abstract: Provided is a solid-state imaging device that includes a first substrate that has one principal surface on which a pixel portion in which pixels are arranged is formed, a second substrate which is bonded to a surface of the first substrate opposed to the one principal surface and in which an opening is provided in a partial region in a surface opposed to a bonding surface to the first substrate is provided. The solid-state imaging device further includes at least one sub-chip inside the opening so as not to protrude from the opening and in which a circuit having a predetermined function is formed.

Abstract: Provided is a solid-state imaging device that includes a first substrate that has one principal surface on which a pixel portion in which pixels are arranged is formed, a second substrate which is bonded to a surface of the first substrate opposed to the one principal surface and in which an opening is provided in a partial region in a surface opposed to a bonding surface to the first substrate is provided. The solid-state imaging device further includes at least one sub-chip inside the opening so as not to protrude from the opening and in which a circuit having a predetermined function is formed.

Abstract: Provided is a solid-state imaging device that includes a first substrate that has one principal surface on which a pixel portion in which pixels are arranged is formed, a second substrate which is bonded to a surface of the first substrate opposed to the one principal surface and in which an opening is provided in a partial region in a surface opposed to a bonding surface to the first substrate is provided. The solid-state imaging device further includes at least one sub-chip inside the opening so as not to protrude from the opening and in which a circuit having a predetermined function is formed.

Abstract: An imaging device according to an embodiment of the present disclosure including a first chip; a support substrate; and a second chip. The support substrate includes an excavated portion in a region opposed to the first chip. The excavated portion has a shape of a recess or a shape of a hole. The second chip is disposed in the excavated portion of the support substrate. The second chip is electrically coupled to the first chip. At least one of the first chip or the second chip has a photoelectric conversion function.

Abstract: A semiconductor device according to an embodiment of the present disclosure includes: a first substrate including a first junction portion; and a second substrate including a second junction portion. The second junction portion is joined to the first junction portion. The first substrate further includes a first multilayer wiring layer in which one surface of a first wiring line faces a first insulating layer and another surface opposed to the one surface is in contact with a second insulating layer. The first multilayer wiring layer is electrically coupled to the first junction portion via the first insulating layer. The first wiring line is formed closest to a junction surface with the second substrate. The second insulating layer has a lower relative dielectric constant than a relative dielectric constant of the first insulating layer.

Abstract: [Problem] Provided is a solid-state imaging device with a higher degree of freedom of the size and layout of chips to be laminated. [Solution] The solid-state imaging device includes: a first substrate that has one principal surface on which a pixel portion in which pixels are arranged is formed; a second substrate which is bonded to a surface of the first substrate opposed to the one principal surface and in which an opening is provided in a partial region in a surface opposed to a bonding surface to the first substrate is provided; and at least one sub-chip which is provided inside the opening so as not to protrude from the opening and in which a circuit having a predetermined function is formed.

Abstract: A body support device includes: a first support part that is attached to a thigh back of a wearer so that a first end thereof is located close to a hip of the wearer and a second end thereof is located close to a knee of the wearer; a second support part that is attached to a shin of the wearer so that a first end thereof is located close to the knee of the wearer and a second end thereof is located close to a foot of the wearer; a grounding part located close to the foot of the wearer; a first rotary part that connects the second end of the first support part with the first end of the second support part and rotates the first and second support parts; and a second rotary part that connects the second end of the second support part with an upper end of the grounding part and rotates the second support part and the grounding part.

Abstract: A method of producing a GaAs single crystal having high carrier concentration and high crystallinity and to provide a GaAs single crystal wafer using such a GaAs single crystal. In the method of producing a GaAs single crystal, a vertical boat method is performed with a crucible receiving a seed crystal, a Si material, a GaAs material serving as an impurity, solid silicon dioxide, and a boron oxide material, thereby growing a GaAs single crystal.

Abstract: A method of producing a GaAs single crystal having high carrier concentration and high crystallinity and to provide a GaAs single crystal wafer using such a GaAs single crystal. In the method of producing a GaAs single crystal, a vertical boat method is performed with a crucible receiving a seed crystal, a Si material, a GaAs material serving as an impurity, solid silicon dioxide, and a boron oxide material, thereby growing a GaAs single crystal.

Abstract: Disclosed herein is a semiconductor memory device including a plurality of memory cells including first and second inverters each having first and second driver transistors and first and second load transistors and including first and second memory node, and first and second transfer transistors. The of the first and second transfer transistors is connected to each of the first and memory nodes respectively. The memory cell is connected to a bit line and complementary bit line via the first and second transfer transistors respectively wherein a supply voltage applied to the bit line and the complementary bit line is lower than a supply voltage applied to the load transistors, and at least a memory-node-side end of a gate insulating film of the first driver transistor, second driver transistor, first load transistor, and the second load transistor have a thickness larger than a thickness of a gate insulating film of the other part.

Abstract: A therapeutic-substance carrying/administering appliance includes a cylindrical outer sheath; a slide member installed in the cylindrical outer sheath to be slidable therein; and a sheet supporting member, connected to a distal end of the slide member and made of a resilient material, for supporting a sheet-shaped therapeutic substance. The sheet supporting member is held in a flat unrolled shape in a free state in which the sheet supporting member projects outwardly from a distal end of the cylindrical outer sheath. When the sheet supporting member is in the free state, sliding the slide member in a retracting direction causes the sheet supporting member to contact the distal end of the cylindrical outer sheath, and subsequently further moving the slide member in the retracting direction causes the sheet supporting member to be retracted into the cylindrical outer sheath while being deformed into a tubular shape.

Abstract: Disclosed herein is a semiconductor memory device including a plurality of memory cells including first and second inverters each having first and second driver transistors and first and second load transistors and including first and second memory node, and first and second transfer transistors. The of the first and second transfer transistors is connected to each of the first and memory nodes respectively. The memory cell is connected to a bit line and complementary bit line via the first and second transfer transistors respectively wherein a supply voltage applied to the bit line and the complementary bit line is lower than a supply voltage applied to the load transistors, and at least a memory-node-side end of a gate insulating film of the first driver transistor, second driver transistor, first load transistor, and the second load transistor have a thickness larger than a thickness of a gate insulating film of the other part.

Abstract: A therapeutic-substance carrying/administering appliance includes a cylindrical outer sheath; a slide member installed in the cylindrical outer sheath to be slidable therein; and a sheet supporting member, connected to a distal end of the slide member and made of a resilient material, for supporting a sheet-shaped therapeutic substance. The sheet supporting member is held in a flat unrolled shape in a free state in which the sheet supporting member projects outwardly from a distal end of the cylindrical outer sheath. When the sheet supporting member is in the free state, sliding the slide member in a retracting direction causes the sheet supporting member to contact the distal end of the cylindrical outer sheath, and subsequently further moving the slide member in the retracting direction causes the sheet supporting member to be retracted into the cylindrical outer sheath while being deformed into a tubular shape.

Abstract: A method includes the steps of: implanting boron into a surface region of a silicon substrate to form a p+ diffused region; implanting indium into the surface of the p+ diffused region, to form an indium-implanted layer; forming a contact metal layer on the indium-implanted layer; and reacting silicon in the silicon substrate including the indium-implanted layer with metal in the contact metal layer to form a titanium silicide layer.

Abstract: In a semiconductor device of a polysilicon gate electrode structure having three or more different Fermi levels, a P type polysilicon having a lowest Fermi level is disposed on a first N type surface channel MOS transistor. A first N type polysilicon having a highest Fermi level is disposed on a second N type surface channel MOS transistor. A second N type polysilicon having an intermediate Fermi level between the highest and the lowest Fermi levels and doped with both an N type impurity and a P type impurity is disposed on a P channel MOS transistor.

Abstract: A method includes the steps of: implanting boron into a surface region of a silicon substrate to form a p+ diffused region; implanting indium into the surface of the p+ diffused region, to form an indium-implanted layer; forming a contact metal layer on the indium-implanted layer; and reacting silicon in the silicon substrate including the indium-implanted layer with metal in the contact metal layer to form a titanium silicide layer.

Abstract: In a semiconductor device of a polysilicon gate electrode structure having three or more different Fermi levels, a P type polysilicon having a lowest Fermi level is disposed on a first N type surface channel MOS transistor. A first N type polysilicon having a highest Fermi level is disposed on a second N type surface channel MOS transistor. A second N type polysilicon having an intermediate Fermi level between the highest and the lowest Fermi levels and doped with both an N type impurity and a P type impurity is disposed on a P channel MOS transistor.