Abstract: A semiconductor device includes a PMOS transistor region in which a PMOS transistor is fabricated, an N well diffusion layer region in which an N well diffusion layer is fabricated, a P well diffusion layer region in which a P well diffusion layer is fabricated, and at least one NMOS transistor region in which an NMOS transistor is fabricated, wherein each of the NMOS transistor region and the P well diffusion layer region includes a pocket boron region in which pocket boron is implanted, and a P well is formed across the P well diffusion layer region and the NMOS transistor region such that the P well is electrically connected to the P well diffusion layer region.

Abstract: It is intended to enable simultaneous formation of concave capacitor storage electrodes and a convex bit contact plug electrode and thereby makes it possible to reduce spaces of margins for alignment errors by decreasing the number of lithography steps. Gate electrodes are formed on a p-well in such a manner that the gate electrode interval in storage electrode forming portions is longer than that in a bit contact plug forming portion, and sidewalls are then formed. An SiO2 film is deposited, storage electrode forming holes and a bit contact plug forming holes are formed therein, and then a polysilicon film is deposited. Another SiO2 film is deposited on the polysilicon film and etched back. Then, the polysilicon film is etched back. After etching of the SiO2 films, capacitor insulating films and counter electrodes are formed and a bit line is also formed.

Abstract: A semiconductor device is disclosed including an insulated gate field effect transistor (IGFET) having a gate insulating layer (2), a gate electrode (3), and a source-drain layer (5). The IGFET may include a bird's beak insulating film (4) in a region in which the gate insulating layer (2) overlaps the source-drain layer (5). The bird's beak insulating film (4) may have a thickness that is greater than the gate insulating film (2). In this way, inter-band tunneling may be reduced. A plurality of IGFETs may include bird's beak insulating films having different configurations in accordance with operating conditions of the circuit in which the particular IGFET is included.

Abstract: A semiconductor device of the present invention has a plurality of capacitors having a cylindrical lower electrode which is formed along the side and the bottom surface of a recess formed in an insulator film over a semiconductor substrate and which is made of silicon having a lot of grained silicon on the surface, and a protector film with resistance to etching of a silicon oxide film is formed at least on the upper surface of the insulator film positioned between the adjacent lower electrodes.

Abstract: A semiconductor device is disclosed including a memory cell region (I) and a peripheral region (II). The memory cell region (I) may have a more densely arranged gate spacing than the peripheral region (II). The memory cell region (I) may include an interlayer insulating film (206) and peripheral region (II) may include an interlayer insulating film (208). The interlayer insulating film (208) in the peripheral region (II) may have a lower concentration of boron and phosphorus than the interlayer insulating film (206) in the memory cell region (I). The concentration of boron in the interlayer insulating film (208) in the peripheral region (II) may be less than 11 mole percent and the concentration of phosphorus may be less than 6 mole percent. In this way, boron and phosphorus may be prevented from diffusing into the substrate while filling properties of the interlayer insulating film may be sufficient.

Abstract: It is intended to enable simultaneous formation of concave capacitor storage electrodes and a convex bit contact plug electrode and thereby makes it possible to reduce spaces of margins for alignment errors by decreasing the number of lithography steps. Gate electrodes are formed on a p-well in such a manner that the gate electrode interval in storage electrode forming portions is longer than that in a bit contact plug forming portion, and sidewalls are then formed. An SiO2 film is deposited, storage electrode forming holes and a bit contact plug forming holes are formed therein, and then a polysilicon film is deposited. Another SiO2 film is deposited on the polysilicon film and etched back. Then, the polysilicon film is etched back. After etching of the SiO2 films, capacitor insulating films and counter electrodes are formed and a bit line is also formed.

Abstract: A semiconductor device is disclosed including an insulated gate field effect transistor (IGFET) having a gate insulating layer (2), a gate electrode (3), and a source-drain layer (5). The IGFET may include a bird's beak insulating film (4) in a region in which the gate insulating layer (2) overlaps the source-drain layer (5). The bird's beak insulating film (4) may have a thickness that is greater than the gate insulating film (2). In this way, inter-band tunneling may be reduced. A plurality of IGFETs may include bird's beak insulating films having different configurations in accordance with operating conditions of the circuit in which the particular IGFET is included.

Abstract: An interlayer insulating film and a first insulating film are formed on a semiconductor substrate. A resist is applied on the first insulating film and then patterning the same so that an opening at an area to form a contact hole has a diameter greater than the width of an opening at an area to form a wiring groove or that an opening at an area to form a deep contact hole is greater in diameter than an opening at an area to form a shallow contact hole. This allows a contact hole and a wiring groove, or a deep contact hole and a shallow contact hole, to be formed by a single photolithographic process.

Abstract: A semiconductor apparatus (010) is disclosed that includes a gate electrode formed over an active area and isolation area that can address adverse current properties that may result in a subthreshold “hump” in a gate voltage (VG)-drain current (ID) response. A first embodiment (010) may include an active area (016) formed adjacent to an isolation area (018). A gate insulator (014) may be formed over active area (016). A gate electrode (020) can be formed over an active area (016) and an isolation area (018). A gate electrode (020) may include end portions (020a) formed in the vicinity of an active area (016)/isolation area (018) interface, and a central portion (020b) formed between end portions (020a). End portions (020a) may be doped differently than a central portion (020b) to effectively compensate for lower threshold voltages in such areas. End portions (020a) may be doped to a conductivity type that is different than a central portion (020b) and the same as a channel region.

Abstract: The thickness of the silicon oxide film covering the upper surface of the word lines 111 is thinner than the thickness of the insulation film spacer 127a covering the side of the gate electrode, and in reflection of this phenomenon, the step of the upper surface of the BPSG film 133 becomes smaller than 1/2 of the depth of focus DOF of the KrF excimer laser and bit lines 137a are formed which have a narrower width and interval than the wavelength of the KrF excimer laser free from the disconnection and the short circuit. As a consequence, bit lines have narrower widths and interval than the wavelength of the exposure light without sacrificing the productivity.

Abstract: A magnetic recording/reproducing apparatus incorporating a clogging detector includes comparator for comparing with a predetermined value an absolute value of signals which are produced by reproducing recorded signals immediately after recording. Clogging signals may be supplied to cleaner for cleaning heads when the absolute value is less than the predetermined value.