Abstract: The present invention relates to improvements in erasing a flash memory. An object of the present invention is to shorten the erasing time. During pre-erase writing, at least either word lines or bit lines are selected in units of multiple lines at a time, and data are written in multiple selective transistors simultaneously.

Abstract: An exclusive OR circuit includes a first series circuit in which a source of a first pMIS transistor is connected to a positive-voltage power supply line. A drain of the first pMIS transistor is connected to a drain of a first nMIS transistor via a second nMIS transistor. The source of the first nMIS transistor is connected to a low-voltage power supply line via a fourth nMIS transistor. A second series circuit has a drain of a third nMIS transistor connected to a high-voltage power supply line via a second pMIS transistor. The source of the third nMIS transistor is connected to the source of a third pMIS transistor. The drain of the third pMIS transistor is connected to the low-voltage power supply line via a fourth pMIS transistor. The gates of the first and third nMIS transistors and the first and third pMIS transistors are connected to one another and provided with a first input.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cell parts which are arranged in an array, where each of the memory cell parts are made up of an electrically erasable programmable non-volatile memory cell and a volatile random access memory cell, a mode selection circuit for transferring data stored in the volatile random access memory cell into the electrically erasable programmable non-volatile memory cell for each of the memory cell parts in response to a store signal which specifies a store mode in which the data are stored in the electrically erasable programmable non-volatile memory cell of each of the memory cell parts, and a memory part for storing at least predetermined bits of the external memory address in response to the store signal.

Abstract: This invention relates to an X-ray image sensor formed by fitting and integrating a fiber plate equipped with a phosphor layer to and with a solid state imaging device, and to an X-ray image sensor which uses a material containing chromium (Cr) adapting to the spectral sensitivity characteristics of a silicon type solid state imaging device as the material of the phosphor layer.

Abstract: In an X-ray image sensor wherein a fiber optic plate having formed thereon a phosphor layer is fitted to and integrated with a solid state imaging device. The present invention relates to an X-ray image sensor using, as the phosphor material, a material to which neodymium (Nd) having a light emission band outside the wavelength range that is absorbed and decreased by coloring damage generated by X-rays is added.

Abstract: A semiconductor memory device includes a memory cell array; a sense amplifying circuit, operatively connected to the memory cell array, for sensing the information bits and the check bits; a latch circuit, operatively connected to the sense amplifying circuit, for latching the information bits and the check bits sensed by the sense amplifying circuit; and a circuit for correcting an error in logical level in the information bits.The latch circuit latches the logical level of the bit signal at a predetermined time after a change in an address signal. Thus, regardless of whether or not a time at which the logical level of the bit signal of the sense amplifying circuit is settled coincides, the influence is not exerted on the operation of the subsequent error correcting circuit. As a result, it is possible to prevent the appearance of a hazard in the output data and, accordingly, to realize a perfect ECC relief, while increasing a reliability in the reading operation as a device.