Abstract: A communication device includes a memory and a processor coupled to the memory. The processor executes a process including calculating an amount of electricity available in a second device while a first communication unit and a second communication unit with each other, determining a first generation unit to be a generation unit, when the amount of electricity thus calculated is smaller than a predetermined amount, out of the first generation unit that generates navigation information based on information acquired by an information acquisition unit and a second generation unit, and controlling the second device so as to stop supplying power to the second generation unit and to output the navigation information generated by the first generation unit when the first generation unit is determined.

Abstract: Design and verification support related to integrated circuits that includes acquiring a first use case diagram representing a function of an object subject to design and verification and an activity diagram representing a processing procedure of the object; analyzing a structure of the activity diagram acquired at the acquiring step; converting the activity diagram to a second use case diagram representing a function of the object, based on the structure analyzed at the analyzing; verifying uniformity of the first use case diagram and the second use case diagram; and outputting a verification result obtained at the verifying uniformity.

Abstract: In a design verification apparatus, a priority resolver selects one or more verification datasets for verifying a procedure described in a design specification of a target product, in response to a verification request for that procedure. The priority resolver determines a priority score of each parameter that the selected verification datasets specify as a constraint on the procedure. A verification order resolver determines a verification order of the selected verification datasets, based on the priority scores determined by the priority resolver. An output processor produces data identifying the verification datasets, together with indication of the determined verification order.

Abstract: A verification target register to be verified is specified from a configuration of a verification target circuit, and patterns requiring verification are extracted as a coverage standard with regard to the specified verification target register. When the patterns are extracted, a DIRW matrix is prepared to indicate possibly occurring state transitions among four states Declare, Initialize, Read, and Write in the register included in the verification target circuit, and used to decide two coverage standards, a matrix coverage standard and an implementation coverage standard.

Abstract: A verification support apparatus and method are provided. The verification support apparatus executing a simulation controlling a communication between a first hardware model in communication with a bus model and adapted to the same first specifications as the bus model, and a second hardware model in communication with the bus model and adapted to second specifications differing from those of the bus model, the apparatus includes a reception unit that receives data based on the second specifications from the second hardware model, a conversion unit that, based on the first specifications, converts the data received by the reception unit into data adapted to the first specifications; and a transmission unit that transmits the data converted by the conversion unit, via the bus model, to a hardware model which is a transmission destination.

Abstract: An information processing apparatus includes a first detector that detects a scheduled starting time of an event to be corrected and executed at the current time or thereafter; a second detector that detects in processing contents differing from that of the event detected by the first detector, a scheduled starting time of each event to be executed at the current time or thereafter; a calculator that calculates the difference between the scheduled starting time detected by the first detector and each scheduled starting time detected by the second detector; a determiner that determines a target event for the event to be corrected, based on the calculated differences; and a corrector that corrects the scheduled starting time of the event to be corrected such that an interval becomes short between the scheduled starting time of the event to be corrected and the scheduled starting time of the target event.

Abstract: A wireless communication device includes: a first wireless communication unit configured to receive a beacon signal when the first wireless communication unit is connected to a first wireless communication network; a second wireless communication unit configured to perform data communication through a second wireless communication network when the first wireless communication unit is not connected to the first wireless communication network; and a control unit configured to detect, from a signal from the first wireless communication network, a parameter concerning intervals at which the first wireless communication unit receives the beacon signal, and configured to perform control, based on the detected parameter, as to whether or not to disconnect connection to the first wireless communication network.

Abstract: A computer-readable recording medium stores therein a verification support program that causes a computer to execute receiving a hardware description of a combinational circuit to be verified; extracting, from the hardware description, a conditional branch description expressing conditional branch processing; identifying, from among conditional branch descriptions extracted at the extracting of a conditional branch description and based on a description sequence in the hardware description, a combination of conditional branch descriptions having a hierarchical relation; extracting, from among combinations of conditional branch descriptions identified at the identifying, a combination having a potential to satisfy a specified condition; creating a simulation program that causes the specified condition for the conditional branch descriptions included in the combination extracted at the extracting of the combination to be satisfied; and outputting, as assertion information of the combinational circuit, the simul

Abstract: A computer-readable recording medium stores therein a verification support program that causes a computer to execute receiving a hardware description of a sequential circuit to be verified and a timing specification that indicates a timing constraint in the hardware description; converting the hardware description into a control flow graph that expresses a flow of control in the sequential circuit; indentifying, from the control flow graph and as a combination of conditional branch descriptions having a hierarchical relation, conditional branch descriptions that are connected in parallel; extracting, from among identified combinations of conditional branch descriptions, a combination having a potential to satisfy specified conditions; creating a simulation program that, at a timing satisfying the timing specification, causes the conditional branch descriptions included in the extracted combination to satisfy the specified conditions; and outputting, as assertion information of the sequential circuit, the simu

Abstract: A non-transitory, computer-readable recording medium stores therein a verification support program that causes a computer to execute identifying from a finite state machine model related to a circuit-under-test, an input count of transitions to a transition-end state and an output count of transitions from the transition-end state; determining the transition-end state to be a record/restore subject, if the identified output transition>the identified input transition count; embedding record-instruction information causing the record/restore subject to be recorded to a database, if a first element causing transition to the record/restore subject is included in a first test scenario that is in a test scenario group related to the circuit-under-test; and embedding restore-instruction information causing the record-restore subject to be restored from the database, if a second element causing transition to the record-restore subject is included in a series of elements making up a second test scenario that is in

Abstract: A verification target register to be verified is specified from a configuration of a verification target circuit, and patterns requiring verification are extracted as a coverage standard with regard to the specified verification target register. When the patterns are extracted, a DIRW matrix is prepared to indicate possibly occurring state transitions among four states Declare, Initialize, Read, and Write in the register included in the verification target circuit, and used to decide two coverage standards, a matrix coverage standard and an implementation coverage standard.

Abstract: In a verification supporting apparatus, a recording unit records a DIRW matrix in which a state transition possibly occurring in a register of a circuit to be verified and information concerning validity of a path corresponding to the state transition are set and an acquiring unit acquires a control data flow graph that includes a control flow graph having a data flow graph written therein. When a register is designated for verification, a data flow graph having described therein the designated register is extracted from the control data flow graph. From the data flow graph extracted, a path indicating the flow of data concerning the register is extracted. The state transition of the path extracted is identified and if the state transition is determined to be is set in the DIRW matrix, information concerning the validity set in the DIRW matrix and the path are correlated, and output.

Abstract: A verification target register to be verified is specified from a configuration of a verification target circuit, and patterns requiring verification are extracted as a coverage standard with regard to the specified verification target register. When the patterns are extracted, a DIRW matrix is prepared to indicate possibly occurring state transitions among four states Declare, Initialize, Read, and Write in the register included in the verification target circuit, and used to decide two coverage standards, a matrix coverage standard and an implementation coverage standard.

Abstract: An apparatus for verifying a specification includes a use-case extracting unit, a first setting unit, an operation extracting unit, a second setting unit, and a determining unit. The use-case extracting unit extracts an unprocessed use case from specification data. The first setting unit sets a condition based on a precondition, a postcondition, and an invariant condition for the use case. The operation extracting unit selects an event flow of an unprocessed path from the specification data and extracts an unprocessed operation (description) from the event flow selected. The second setting unit sets a precondition and a postcondition for the operation based on the extracted operation (description). The determining unit determines whether the invariant condition is valid.

Abstract: In a design verification apparatus, a priority resolver selects one or more verification datasets for verifying a procedure described in a design specification of a target product, in response to a verification request for that procedure. The priority resolver determines a priority score of each parameter that the selected verification datasets specify as a constraint on the procedure. A verification order resolver determines a verification order of the selected verification datasets, based on the priority scores determined by the priority resolver. An output processor produces data identifying the verification datasets, together with indication of the determined verification order.

Abstract: A method of generating a scenario includes generating a specification model by describing a specification in a predetermined descriptive language, extracting a plurality of operations from the specification model, generating a plurality of operation descriptions, each of which corresponds to one of the operations and includes an operation name and a constraint condition, generating at least one cause-effect graph that combines the operations based on the operation descriptions, and extracting as a scenario a series of operations from the cause-effect graph.

Abstract: A verification support apparatus that verifies operation of a circuit includes a receiving unit, a detecting unit, and a determining unit. The receiving unit receives implementation description data of the circuit. Based on the implementation description data, the detecting unit detects a functional block that is in the circuit and includes an external input terminal that receives an external input signal. Based on a detection result of the detecting unit, the determining unit determines the functional block to verify an abnormal-event operation. The abnormal-event operation is an operation that differs from an operation implementing a function of the circuit.

Abstract: A verification support apparatus and method are provided. The verification support apparatus executing a simulation controlling a communication between a first hardware model in communication with a bus model and adapted to the same first specifications as the bus model, and a second hardware model in communication with the bus model and adapted to second specifications differing from those of the bus model, the apparatus includes a reception unit that receives data based on the second specifications from the second hardware model, a conversion unit that, based on the first specifications, converts the data received by the reception unit into data adapted to the first specifications; and a transmission unit that transmits the data converted by the conversion unit, via the bus model, to a hardware model which is a transmission destination.

Abstract: An apparatus for supporting a verification for each of a plurality of functions of a target object, includes: a receiving unit that receives a use case diagram that includes a plurality of use cases each of which corresponding to each of the functions; an extracting unit that extracts a relation between the use cases from the use case diagram; and a setting unit that sets a priority of verification for each of the use cases based on the relation.

Abstract: A computer-readable recording medium stores therein a verification support program that causes a computer to execute receiving a hardware description of a sequential circuit to be verified and a timing specification that indicates a timing constraint in the hardware description; converting the hardware description into a control flow graph that expresses a flow of control in the sequential circuit; indentifying, from the control flow graph and as a combination of conditional branch descriptions having a hierarchical relation, conditional branch descriptions that are connected in parallel; extracting, from among identified combinations of conditional branch descriptions, a combination having a potential to satisfy specified conditions; creating a simulation program that, at a timing satisfying the timing specification, causes the conditional branch descriptions included in the extracted combination to satisfy the specified conditions; and outputting, as assertion information of the sequential circuit, the simu