Abstract: A computer-readable recording medium stores therein a verification support program that causes a computer to execute receiving a hardware description of a combinational circuit to be verified; extracting, from the hardware description, a conditional branch description expressing conditional branch processing; identifying, from among conditional branch descriptions extracted at the extracting of a conditional branch description and based on a description sequence in the hardware description, a combination of conditional branch descriptions having a hierarchical relation; extracting, from among combinations of conditional branch descriptions identified at the identifying, a combination having a potential to satisfy a specified condition; creating a simulation program that causes the specified condition for the conditional branch descriptions included in the combination extracted at the extracting of the combination to be satisfied; and outputting, as assertion information of the combinational circuit, the simul

Abstract: A verification assisting apparatus for assisting a matching check between a specification and implementation of an object includes: an obtaining unit that obtains a specification description including elements executed to realize functions of the object and restricting conditions of the elements to realize the functions, and an implementation description concerning the functions; a creating unit that creates a graph structure including, as nodes, the elements and the restricting conditions, based on the implementation description; a first correlating unit that correlates nodes in the graph structure with the implementation description; a second correlating unit that correlates a node in the graph structure with the specification description, by detecting the node in the structure using a description concerning the element or the restricting condition in the specification description; and an outputting unit that outputs the correlation results.

Abstract: A computer-readable recording medium stores therein a verification support program that causes a computer to execute selecting arbitrarily a use case from a use case diagram for a verification target; extracting a precondition and a postcondition of the use case selected at the selecting; and converting, to a Kripke model, a finite state machine model corresponding to the use case selected at the selecting. The verification support program further causes the computer to execute specifying, based on the precondition and the postcondition extracted at the extracting, a Kripke initial state, a Kripke precondition, and a Kripke postcondition of the Kripke model obtained at the converting; and generating, based on the Kripke precondition and the Kripke postcondition specified at the specifying, a Kripke property of the use case selected at the selecting.

Abstract: A verification target register to be verified is specified from a configuration of a verification target circuit, and patterns requiring verification are extracted as a coverage standard with regard to the specified verification target register. When the patterns are extracted, a DIRW matrix is prepared to indicate possibly occurring state transitions among four states Declare, Initialize, Read, and Write in the register included in the verification target circuit, and used to decide two coverage standards, a matrix coverage standard and an implementation coverage standard.

Abstract: In a verification supporting apparatus, a recording unit records a DIRW matrix in which a state transition possibly occurring in a register of a circuit to be verified and information concerning validity of a path corresponding to the state transition are set and an acquiring unit acquires a control data flow graph that includes a control flow graph having a data flow graph written therein. When a register is designated for verification, a data flow graph having described therein the designated register is extracted from the control data flow graph. From the data flow graph extracted, a path indicating the flow of data concerning the register is extracted. The state transition of the path extracted is identified and if the state transition is determined to be is set in the DIRW matrix, information concerning the validity set in the DIRW matrix and the path are correlated, and output.

Abstract: A verification support apparatus that verifies operation of a circuit includes a receiving unit, a detecting unit, and a determining unit. The receiving unit receives implementation description data of the circuit. Based on the implementation description data, the detecting unit detects a functional block that is in the circuit and includes an external input terminal that receives an external input signal. Based on a detection result of the detecting unit, the determining unit determines the functional block to verify an abnormal-event operation. The abnormal-event operation is an operation that differs from an operation implementing a function of the circuit.

Abstract: Design and verification support related to integrated circuits that includes acquiring a first use case diagram representing a function of an object subject to design and verification and an activity diagram representing a processing procedure of the object; analyzing a structure of the activity diagram acquired at the acquiring step; converting the activity diagram to a second use case diagram representing a function of the object, based on the structure analyzed at the analyzing; verifying uniformity of the first use case diagram and the second use case diagram; and outputting a verification result obtained at the verifying uniformity.

Abstract: A method of generating a scenario includes generating a specification model by describing a specification in a predetermined descriptive language, extracting a plurality of operations from the specification model, generating a plurality of operation descriptions, each of which corresponds to one of the operations and includes an operation name and a constraint condition, generating at least one cause-effect graph that combines the operations based on the operation descriptions, and extracting as a scenario a series of operations from the cause-effect graph.

Abstract: An apparatus for verifying a specification includes a use-case extracting unit, a first setting unit, an operation extracting unit, a second setting unit, and a determining unit. The use-case extracting unit extracts an unprocessed use case from specification data. The first setting unit sets a condition based on a precondition, a postcondition, and an invariant condition for the use case. The operation extracting unit selects an event flow of an unprocessed path from the specification data and extracts an unprocessed operation (description) from the event flow selected. The second setting unit sets a precondition and a postcondition for the operation based on the extracted operation (description). The determining unit determines whether the invariant condition is valid.

Abstract: An apparatus for supporting a verification for each of a plurality of functions of a target object, includes: a receiving unit that receives a use case diagram that includes a plurality of use cases each of which corresponding to each of the functions; an extracting unit that extracts a relation between the use cases from the use case diagram; and a setting unit that sets a priority of verification for each of the use cases based on the relation.