Patents by Inventor Ryosuke Watanabe

Ryosuke Watanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9318617
    Abstract: It is an object to provide a highly reliable semiconductor device with good electrical characteristics and a display device including the semiconductor device as a switching element. In a transistor including an oxide semiconductor layer, a needle crystal group provided on at least one surface side of the oxide semiconductor layer grows in a c-axis direction perpendicular to the surface and includes an a-b plane parallel to the surface, and a portion except for the needle crystal group is an amorphous region or a region in which amorphousness and microcrystals are mixed. Accordingly, a highly reliable semiconductor device with good electrical characteristics can be formed.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: April 19, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masayuki Sakakura, Ryosuke Watanabe, Junichiro Sakata, Kengo Akimoto, Akiharu Miyanaga, Takuya Hirohashi, Hideyuki Kishida
  • Patent number: 9299855
    Abstract: A semiconductor device includes a semiconductor layer, a gate electrode overlapping with the semiconductor layer, a first gate insulating layer between the semiconductor layer and the gate electrode, and a second gate insulating layer between the first gate insulating layer and the gate electrode. The first gate insulating layer includes an oxide in which the nitrogen content is lower than or equal to 5 at. %, and the second gate insulating layer includes charge trap states.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: March 29, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Takuya Hirohashi, Masahiro Takahashi, Motoki Nakashima, Ryosuke Watanabe, Masashi Tsubuku
  • Patent number: 9275875
    Abstract: An object is to provide a semiconductor device including an oxide semiconductor, which has stable electrical characteristics and high reliability. In a manufacturing process of a bottom-gate transistor including an oxide semiconductor layer, heat treatment in an atmosphere containing oxygen and heat treatment in vacuum are sequentially performed for dehydration or dehydrogenation of the oxide semiconductor layer. In addition, irradiation with light having a short wavelength is performed concurrently with the heat treatment, whereby elimination of hydrogen, OH, or the like is promoted. A transistor including an oxide semiconductor layer on which dehydration or dehydrogenation treatment is performed through such heat treatment has improved stability, so that variation in electrical characteristics of the transistor due to light irradiation or a bias-temperature stress (BT) test is suppressed.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: March 1, 2016
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD
    Inventors: Shunpei Yamazaki, Ryosuke Watanabe, Suzunosuke Hiraishi, Junichiro Sakata
  • Patent number: 9214563
    Abstract: It is an object to provide a highly reliable semiconductor device with good electrical characteristics and a display device including the semiconductor device as a switching element. In a transistor including an oxide semiconductor layer, a needle crystal group provided on at least one surface side of the oxide semiconductor layer grows in a c-axis direction perpendicular to the surface and includes an a-b plane parallel to the surface, and a portion except for the needle crystal group is an amorphous region or a region in which amorphousness and microcrystals are mixed. Accordingly, a highly reliable semiconductor device with good electrical characteristics can be formed.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: December 15, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masayuki Sakakura, Ryosuke Watanabe, Junichiro Sakata, Kengo Akimoto, Akiharu Miyanaga, Takuya Hirohashi, Hideyuki Kishida
  • Publication number: 20150349133
    Abstract: An oxide semiconductor stacked film which does not easily cause a variation in electrical characteristics of a transistor and has high stability is provided. Further, a transistor which includes the oxide semiconductor stacked film in its channel formation region and has stable electrical characteristics is provided. An oxide semiconductor stacked film includes a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer which are sequentially stacked and each of which contains indium, gallium, and zinc. The content percentage of indium in the second oxide semiconductor layer is higher than that in the first oxide semiconductor layer and the third oxide semiconductor layer, and the absorption coefficient of the oxide semiconductor stacked film, which is measured by the CPM, is lower than or equal to 3×10?3/cm in an energy range of 1.5 eV to 2.3 eV.
    Type: Application
    Filed: July 30, 2015
    Publication date: December 3, 2015
    Inventors: Shunpei YAMAZAKI, Masashi TSUBUKU, Ryosuke WATANABE, Masashi OOTA, Noritaka ISHIHARA, Koki INOUE
  • Publication number: 20150287660
    Abstract: Thin film integrated circuits are peeled from a substrate and the peeled thin film integrated circuits are sealed, efficiently in order to improve manufacturing yields. The present invention provides laminating system comprising transporting means for transporting a substrate provided with a plurality of thin film integrated circuits; first peeling means for bonding first surfaces of the thin film integrated circuits to a first sheet member to peel the thin film integrated circuits from the substrate; second peeling means for bonding second surfaces of the thin film integrated circuits to a second sheet member to peel the thin film integrated circuits from the first sheet member; and sealing means for interposing the thin film integrated circuits between the second sheet member and a third sheet member to seal the thin film integrated circuit with the second sheet member and the third sheet member.
    Type: Application
    Filed: May 28, 2015
    Publication date: October 8, 2015
    Inventors: Ryosuke WATANABE, Naoto KUSUMOTO, Osamu NAKAMURA
  • Patent number: 9123573
    Abstract: An oxide semiconductor stacked film which does not easily cause a variation in electrical characteristics of a transistor and has high stability is provided. Further, a transistor which includes the oxide semiconductor stacked film in its channel formation region and has stable electrical characteristics is provided. An oxide semiconductor stacked film includes a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer which are sequentially stacked and each of which contains indium, gallium, and zinc. The content percentage of indium in the second oxide semiconductor layer is higher than that in the first oxide semiconductor layer and the third oxide semiconductor layer, and the absorption coefficient of the oxide semiconductor stacked film, which is measured by the CPM, is lower than or equal to 3×10?3/cm in an energy range of 1.5 eV to 2.3 eV.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: September 1, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masashi Tsubuku, Ryosuke Watanabe, Masashi Oota, Noritaka Ishihara, Koki Inoue
  • Patent number: 9053401
    Abstract: Thin film integrated circuits are peeled from a substrate and the peeled thin film integrated circuits are sealed, efficiently in order to improve manufacturing yields. The present invention provides laminating system comprising transporting means for transporting a substrate provided with a plurality of thin film integrated circuits; first peeling means for bonding first surfaces of the thin film integrated circuits to a first sheet member to peel the thin film integrated circuits from the substrate; second peeling means for bonding second surfaces of the thin film integrated circuits to a second sheet member to peel the thin film integrated circuits from the first sheet member; and sealing means for interposing the thin film integrated circuits between the second sheet member and a third sheet member to seal the thin film integrated circuit with the second sheet member and the third sheet member.
    Type: Grant
    Filed: July 28, 2005
    Date of Patent: June 9, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Ryosuke Watanabe, Naoto Kusumoto, Osamu Nakamura
  • Publication number: 20150104901
    Abstract: It is an object to provide a highly reliable semiconductor device with good electrical characteristics and a display device including the semiconductor device as a switching element. In a transistor including an oxide semiconductor layer, a needle crystal group provided on at least one surface side of the oxide semiconductor layer grows in a c-axis direction perpendicular to the surface and includes an a-b plane parallel to the surface, and a portion except for the needle crystal group is an amorphous region or a region in which amorphousness and microcrystals are mixed. Accordingly, a highly reliable semiconductor device with good electrical characteristics can be formed.
    Type: Application
    Filed: December 18, 2014
    Publication date: April 16, 2015
    Inventors: Shunpei YAMAZAKI, Masayuki SAKAKURA, Ryosuke WATANABE, Junichiro SAKATA, Kengo AKIMOTO, Akiharu MIYANAGA, Takuya HIROHASHI, Hideyuki KISHIDA
  • Publication number: 20150048368
    Abstract: An oxide semiconductor stacked film which does not easily cause a variation in electrical characteristics of a transistor and has high stability is provided. Further, a transistor which includes the oxide semiconductor stacked film in its channel formation region and has stable electrical characteristics is provided. An oxide semiconductor stacked film includes a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer which are sequentially stacked and each of which contains indium, gallium, and zinc. The content percentage of indium in the second oxide semiconductor layer is higher than that in the first oxide semiconductor layer and the third oxide semiconductor layer, and the absorption coefficient of the oxide semiconductor stacked film, which is measured by the CPM, is lower than or equal to 3×10?3/cm in an energy range of 1.5 eV to 2.3 eV.
    Type: Application
    Filed: October 29, 2014
    Publication date: February 19, 2015
    Inventors: Shunpei YAMAZAKI, Masashi TSUBUKU, Ryosuke WATANABE, Masashi OOTA, Noritaka ISHIHARA, Koki INOUE
  • Publication number: 20150050775
    Abstract: An object is to provide a semiconductor device including an oxide semiconductor, which has stable electrical characteristics and high reliability. In a manufacturing process of a bottom-gate transistor including an oxide semiconductor layer, heat treatment in an atmosphere containing oxygen and heat treatment in vacuum are sequentially performed for dehydration or dehydrogenation of the oxide semiconductor layer. In addition, irradiation with light having a short wavelength is performed concurrently with the heat treatment, whereby elimination of hydrogen, OH, or the like is promoted. A transistor including an oxide semiconductor layer on which dehydration or dehydrogenation treatment is performed through such heat treatment has improved stability, so that variation in electrical characteristics of the transistor due to light irradiation or a bias-temperature stress (BT) test is suppressed.
    Type: Application
    Filed: October 31, 2014
    Publication date: February 19, 2015
    Inventors: Shunpei YAMAZAKI, Ryosuke WATANABE, Suzunosuke HIRAISHI, Junichiro SAKATA
  • Publication number: 20150041801
    Abstract: A semiconductor device includes a semiconductor layer, a gate electrode overlapping with the semiconductor layer, a first gate insulating layer between the semiconductor layer and the gate electrode, and a second gate insulating layer between the first gate insulating layer and the gate electrode. The first gate insulating layer includes an oxide in which the nitrogen content is lower than or equal to 5 at. %, and the second gate insulating layer includes charge trap states.
    Type: Application
    Filed: July 31, 2014
    Publication date: February 12, 2015
    Inventors: Shunpei YAMAZAKI, Takuya HIROHASHI, Masahiro TAKAHASHI, Motoki NAKASHIMA, Ryosuke WATANABE, Masashi TSUBUKU
  • Patent number: 8906756
    Abstract: An object is to provide a semiconductor device including an oxide semiconductor, which has stable electrical characteristics and high reliability. In a manufacturing process of a bottom-gate transistor including an oxide semiconductor layer, heat treatment in an atmosphere containing oxygen and heat treatment in vacuum are sequentially performed for dehydration or dehydrogenation of the oxide semiconductor layer. In addition, irradiation with light having a short wavelength is performed concurrently with the heat treatment, whereby elimination of hydrogen, OH, or the like is promoted. A transistor including an oxide semiconductor layer on which dehydration or dehydrogenation treatment is performed through such heat treatment has improved stability, so that variation in electrical characteristics of the transistor due to light irradiation or a bias-temperature stress (BT) test is suppressed.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: December 9, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Ryosuke Watanabe, Suzunosuke Hiraishi, Junichiro Sakata
  • Patent number: 8890159
    Abstract: An oxide semiconductor stacked film which does not easily cause a variation in electrical characteristics of a transistor and has high stability is provided. Further, a transistor which includes the oxide semiconductor stacked film in its channel formation region and has stable electrical characteristics is provided. An oxide semiconductor stacked film includes a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer which are sequentially stacked and each of which contains indium, gallium, and zinc. The content percentage of indium in the second oxide semiconductor layer is higher than that in the first oxide semiconductor layer and the third oxide semiconductor layer, and the absorption coefficient of the oxide semiconductor stacked film, which is measured by the CPM, is lower than or equal to 3×10?3/cm in an energy range of 1.5 eV to 2.3 eV.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: November 18, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masashi Tsubuku, Ryosuke Watanabe, Masashi Oota, Noritaka Ishihara, Koki Inoue
  • Publication number: 20140252345
    Abstract: An oxide semiconductor film having high stability with respect to light irradiation or a semiconductor device having high stability with respect to light irradiation is provided. One embodiment of the present invention is a semiconductor film including an oxide in which light absorption is observed by a constant photocurrent method (CPM) in a wavelength range of 400 nm to 800 nm, and in which an absorption coefficient of a defect level, which is obtained by removing light absorption due to a band tail from the light absorption, is lower than or equal to 5×10?2/cm. Alternatively, a semiconductor device is manufactured using the semiconductor film.
    Type: Application
    Filed: March 4, 2014
    Publication date: September 11, 2014
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masashi TSUBUKU, Ryosuke WATANABE
  • Publication number: 20140220745
    Abstract: It is an object of the invention to improve the production efficiency in sealing a thin film integrated circuit and to prevent the damage and break. Further, it is another object of the invention to prevent a thin film integrated circuit from being damaged in shipment and to make it easier to handle the thin film integrated circuit. The invention provides a laminating system in which rollers are used for supplying a substrate for sealing, receiving IC chips, separating, and sealing. The separation, sealing, and reception of a plurality of thin film integrated circuits can be carried out continuously by rotating the rollers; thus, the production efficiency can be extremely improved. Further, the thin film integrated circuits can be easily sealed since a pair of rollers opposite to each other is used.
    Type: Application
    Filed: March 18, 2014
    Publication date: August 7, 2014
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Ryosuke WATANABE, Hidekazu TAKAHASHI, Takuya TSURUME
  • Publication number: 20140113405
    Abstract: To form an oxide semiconductor film with a low density of localized levels. To improve electric characteristics of a semiconductor device including the oxide semiconductor. After oxygen is added to an oxide film containing In or Ga in contact with an oxide semiconductor film functioning as a channel, heat treatment is performed to make oxygen in the oxide film containing In or Ga transfer to the oxide semiconductor film functioning as a channel, so that the amount of oxygen vacancies in the oxide semiconductor film is reduced. Further, an oxide film containing In or Ga is formed, oxygen is added to the oxide film, an oxide semiconductor film is formed over the oxide film, and then heat treatment is performed.
    Type: Application
    Filed: October 17, 2013
    Publication date: April 24, 2014
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masashi TSUBUKU, Ryosuke WATANABE, Noritaka ISHIHARA, Masashi OOTA
  • Patent number: 8698156
    Abstract: It is an object of the invention to improve the production efficiency in sealing a thin film integrated circuit and to prevent the damage and break. Further, it is another object of the invention to prevent a thin film integrated circuit from being damaged in shipment and to make it easier to handle the thin film integrated circuit. The invention provides a laminating system in which rollers are used for supplying a substrate for sealing, receiving IC chips, separating, and sealing. The separation, sealing, and reception of a plurality of thin film integrated circuits can be carried out continuously by rotating the rollers; thus, the production efficiency can be extremely improved. Further, the thin film integrated circuits can be easily sealed since a pair of rollers opposite to each other is used.
    Type: Grant
    Filed: March 13, 2009
    Date of Patent: April 15, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Ryosuke Watanabe, Hidekazu Takahashi, Takuya Tsurume
  • Publication number: 20140034946
    Abstract: An oxide semiconductor stacked film which does not easily cause a variation in electrical characteristics of a transistor and has high stability is provided. Further, a transistor which includes the oxide semiconductor stacked film in its channel formation region and has stable electrical characteristics is provided. An oxide semiconductor stacked film includes a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer which are sequentially stacked and each of which contains indium, gallium, and zinc. The content percentage of indium in the second oxide semiconductor layer is higher than that in the first oxide semiconductor layer and the third oxide semiconductor layer, and the absorption coefficient of the oxide semiconductor stacked film, which is measured by the CPM, is lower than or equal to 3×10?3/cm in an energy range of 1.5 eV to 2.3 eV.
    Type: Application
    Filed: July 29, 2013
    Publication date: February 6, 2014
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei YAMAZAKI, Masashi TSUBUKU, Ryosuke WATANABE, Masashi OOTA, Noritaka ISHIHARA, Koki INOUE
  • Patent number: 8625085
    Abstract: Even in the case of a sample exhibiting low photoresponse, such as a wide bandgap semiconductor, a measurement method which enables highly accurate CPM measurement is provided. When CPM measurement is performed, photoexcited carriers which are generated by light irradiation of a sample exhibiting low photoresponse such as a wide bandgap semiconductor are instantly removed by application of positive bias voltage to a third electrode which is provided in the sample in addition to two electrodes used for measurement. When the photoexcited carriers are removed, even in the case of the sample exhibiting low photoresponse, the controllability of a photocurrent value is improved and CPM measurement can be performed accurately.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: January 7, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Ryosuke Watanabe, Masashi Tsubuku, Takayuki Inoue