Patents by Inventor Ryosuke Watanabe

Ryosuke Watanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130299827
    Abstract: It is an object to provide a highly reliable semiconductor device with good electrical characteristics and a display device including the semiconductor device as a switching element. In a transistor including an oxide semiconductor layer, a needle crystal group provided on at least one surface side of the oxide semiconductor layer grows in a c-axis direction perpendicular to the surface and includes an a-b plane parallel to the surface, and a portion except for the needle crystal group is an amorphous region or a region in which amorphousness and microcrystals are mixed. Accordingly, a highly reliable semiconductor device with good electrical characteristics can be formed.
    Type: Application
    Filed: July 22, 2013
    Publication date: November 14, 2013
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei YAMAZAKI, Masayuki SAKAKURA, Ryosuke WATANABE, Junichiro SAKATA, Kengo AKIMOTO, Akiharu MIYANAGA, Takuya HIROHASHI, Hideyuki KISHIDA
  • Patent number: 8492758
    Abstract: It is an object to provide a highly reliable semiconductor device with good electrical characteristics and a display device including the semiconductor device as a switching element. In a transistor including an oxide semiconductor layer, a needle crystal group provided on at least one surface side of the oxide semiconductor layer grows in a c-axis direction perpendicular to the surface and includes an a-b plane parallel to the surface, and a portion except for the needle crystal group is an amorphous region or a region in which amorphousness and microcrystals are mixed. Accordingly, a highly reliable semiconductor device with good electrical characteristics can be formed.
    Type: Grant
    Filed: September 22, 2010
    Date of Patent: July 23, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masayuki Sakakura, Ryosuke Watanabe, Junichiro Sakata, Kengo Akimoto, Akiharu Miyanaga, Takuya Hirohashi, Hideyuki Kishida
  • Patent number: 8481377
    Abstract: It is an object to provide a semiconductor device including an oxide semiconductor, in which miniaturization of a transistor is achieved and the concentration of an electric field is relieved. The width of a gate electrode is reduced and a space between a source electrode layer and a drain electrode layer is shortened. By adding a rare gas in a self-alignment manner with the use of a gate electrode as a mask, a low-resistance region in contact with a channel formation region can be provided in an oxide semiconductor layer. Accordingly, even when the width of the gate electrode, that is, the line width of a gate wiring is small, the low-resistance region can be provided with high positional accuracy, so that miniaturization of a transistor can be realized.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: July 9, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Ryosuke Watanabe, Masashi Tsubuku, Shunpei Yamazaki
  • Patent number: 8432996
    Abstract: A transmitter includes an OFDM symbol generator for generating an effective symbol including a plurality of sub-carriers orthogonal to each other in frequency and sequentially generating an OFDM symbol in which a signal in a first period from a first end of the effective symbol is added to a second end of the effective symbol as a guard interval, and a convolution filter for performing an convolution operation on data strings at a plurality of sampling points of the OFDM symbol, wherein when the convolution filter performs a convolution operation on the first data strings including a data string at the first end of the effective symbol, the convolution filter performs the convolution operation on the first data strings in which a data string at the second end of the effective symbol is cyclically added to a data string at the first end.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: April 30, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Ryosuke Watanabe
  • Patent number: 8357567
    Abstract: It is an object of the present invention to provide a manufacturing method of a semiconductor device where a semiconductor element is prevented from being damaged and throughput speed thereof is improved, even in a case of thinning or removing a supporting substrate after forming the semiconductor element over the supporting substrate.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: January 22, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Ryosuke Watanabe
  • Patent number: 8309961
    Abstract: In a channel protected thin film transistor in which a channel formation region is formed using an oxide semiconductor, an oxide semiconductor layer which is dehydrated or dehydrogenated by a heat treatment is used as an active layer, a crystal region including nanocrystals is included in a superficial portion in the channel formation region, and the rest portion is amorphous or is formed of a mixture of amorphousness/non-crystals and microcrystals, where an amorphous region is dotted with microcrystals. By using an oxide semiconductor layer having such a structure, a change to an n-type caused by entry of moisture or elimination of oxygen to or from the superficial portion and generation of a parasitic channel can be prevented and a contact resistance with a source and drain electrodes can be reduced.
    Type: Grant
    Filed: October 4, 2010
    Date of Patent: November 13, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masayuki Sakakura, Ryosuke Watanabe, Junichiro Sakata, Kengo Akimoto, Akiharu Miyanaga, Takuya Hirohashi, Hideyuki Kishida
  • Publication number: 20120256179
    Abstract: To provide a transistor having a favorable electric characteristics and high reliability and a display device including the transistor. The transistor is a bottom-gate transistor formed using an oxide semiconductor for a channel region. An oxide semiconductor layer subjected to dehydration or dehydrogenation through heat treatment is used as an active layer. The active layer includes a first region of a superficial portion microcrystallized and a second region of the rest portion. By using the oxide semiconductor layer having such a structure, a change to an n-type, which is attributed to entry of moisture to the superficial portion or elimination of oxygen from the superficial portion, and generation of a parasitic channel can be suppressed. In addition, contact resistance between the oxide semiconductor layer and source and drain electrodes can be reduced.
    Type: Application
    Filed: June 20, 2012
    Publication date: October 11, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Masayuki SAKAKURA, Ryosuke WATANABE, Junichiro SAKATA, Kengo AKIMOTO, Akiharu MIYANAGA, Takuya HIROHASHI, Hideyuki KISHIDA
  • Publication number: 20120229805
    Abstract: Even in the case of a sample exhibiting low photoresponse, such as a wide bandgap semiconductor, a measurement method which enables highly accurate CPM measurement is provided. When CPM measurement is performed, photoexcited carriers which are generated by light irradiation of a sample exhibiting low photoresponse such as a wide bandgap semiconductor are instantly removed by application of positive bias voltage to a third electrode which is provided in the sample in addition to two electrodes used for measurement. When the photoexcited carriers are removed, even in the case of the sample exhibiting low photoresponse, the controllability of a photocurrent value is improved and CPM measurement can be performed accurately.
    Type: Application
    Filed: February 29, 2012
    Publication date: September 13, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Ryosuke WATANABE, Masashi TSUBUKU, Takayuki INOUE
  • Patent number: 8232181
    Abstract: A manufacturing method of a semiconductor device is provided, which includes a process in which a transistor is formed over a first substrate; a process in which a first insulating layer is formed over the transistor; a process in which a first conductive layer connected to a source or a drain of the transistor is formed; a process in which a second substrate provided with a second insulating layer is arranged so that the first insulating layer is attached to the second insulating layer; a process in which the second insulating layer is separated from the second substrate; and a process in which a third substrate provided with a second conductive layer which functions as an antenna is arranged so that the first conductive layer is electrically connected to the second conductive layer.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: July 31, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Ryosuke Watanabe, Jun Koyama
  • Patent number: 8123896
    Abstract: It is an object of the invention to improve the production efficiency in sealing a thin film integrated circuit and to prevent the damage and break. Further, it is another object of the invention to prevent a thin film integrated circuit from being damaged in shipment and to make it easier to handle the thin film integrated circuit. The invention provides a laminating system in which rollers are used for supplying a substrate for sealing, receiving IC chips, separating, and sealing. The separation, sealing, and reception of a plurality of thin film integrated circuits can be carried out continuously by rotating the rollers; thus, the production efficiency can be extremely improved. Further, the thin film integrated circuits can be easily sealed since a pair of rollers opposite to each other is used.
    Type: Grant
    Filed: May 31, 2005
    Date of Patent: February 28, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Ryosuke Watanabe, Hidekazu Takahashi, Takuya Tsurume
  • Publication number: 20110287591
    Abstract: An object is to provide a semiconductor device including an oxide semiconductor, which has stable electrical characteristics and high reliability. In a manufacturing process of a bottom-gate transistor including an oxide semiconductor layer, heat treatment in an atmosphere containing oxygen and heat treatment in vacuum are sequentially performed for dehydration or dehydrogenation of the oxide semiconductor layer. In addition, irradiation with light having a short wavelength is performed concurrently with the heat treatment, whereby elimination of hydrogen, OH, or the like is promoted. A transistor including an oxide semiconductor layer on which dehydration or dehydrogenation treatment is performed through such heat treatment has improved stability, so that variation in electrical characteristics of the transistor due to light irradiation or a bias-temperature stress (BT) test is suppressed.
    Type: Application
    Filed: May 18, 2011
    Publication date: November 24, 2011
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei YAMAZAKI, Ryosuke WATANABE, Suzunosuke HIRAISHI, Junichiro SAKATA
  • Publication number: 20110204362
    Abstract: It is an object to provide a semiconductor device including an oxide semiconductor, in which miniaturization of a transistor is achieved and the concentration of an electric field is relieved. The width of a gate electrode is reduced and a space between a source electrode layer and a drain electrode layer is shortened. By adding a rare gas in a self-alignment manner with the use of a gate electrode as a mask, a low-resistance region in contact with a channel formation region can be provided in an oxide semiconductor layer. Accordingly, even when the width of the gate electrode, that is, the line width of a gate wiring is small, the low-resistance region can be provided with high positional accuracy, so that miniaturization of a transistor can be realized.
    Type: Application
    Filed: February 14, 2011
    Publication date: August 25, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kengo AKIMOTO, Ryosuke WATANABE, Masashi TSUBUKU, Shunpei YAMAZAKI
  • Publication number: 20110183470
    Abstract: It is an object of the present invention to provide a manufacturing method of a semiconductor device where a semiconductor element is prevented from being damaged and throughput speed thereof is improved, even in a case of thinning or removing a supporting substrate after forming the semiconductor element over the supporting substrate.
    Type: Application
    Filed: March 22, 2011
    Publication date: July 28, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Ryosuke WATANABE
  • Publication number: 20110104859
    Abstract: A manufacturing method of a semiconductor device is provided, which includes a process in which a transistor is formed over a first substrate; a process in which a first insulating layer is formed over the transistor; a process in which a first conductive layer connected to a source or a drain of the transistor is formed; a process in which a second substrate provided with a second insulating layer is arranged so that the first insulating layer is attached to the second insulating layer; a process in which the second insulating layer is separated from the second substrate; and a process in which a third substrate provided with a second conductive layer which functions as an antenna is arranged so that the first conductive layer is electrically connected to the second conductive layer.
    Type: Application
    Filed: November 23, 2010
    Publication date: May 5, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Ryosuke WATANABE, Jun KOYAMA
  • Patent number: 7932126
    Abstract: The area occupied by a photo-sensor element may be reduced and multiple elements may be integrated in a limited area so that the sensor element can have higher output and smaller size. Higher output and miniaturization are achieved by uniting a sensor element using an amorphous semiconductor film (typically an amorphous silicon film) and an output amplifier circuit including a TFT with a semiconductor film having a crystal structure (typically a poly-crystalline silicon film) used as an active layer over a plastic film substrate that can resist the temperature in the process for mounting such as a solder reflow process. A sensor element that can resist bending stress can be obtained.
    Type: Grant
    Filed: January 6, 2009
    Date of Patent: April 26, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junya Maruyama, Toru Takayama, Masafumi Morisue, Ryosuke Watanabe, Eiji Sugiyama, Susumu Okazaki, Kazuo Nishi, Jun Koyama, Takeshi Osada, Takanori Matsuzaki
  • Patent number: 7928510
    Abstract: It is an object of the present invention to provide a manufacturing method of a semiconductor device where a semiconductor element is prevented from being damaged and throughput speed thereof is improved, even in a case of thinning or removing a supporting substrate after forming the semiconductor element over the supporting substrate.
    Type: Grant
    Filed: September 18, 2006
    Date of Patent: April 19, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Ryosuke Watanabe
  • Publication number: 20110084266
    Abstract: In a channel protected thin film transistor in which a channel formation region is formed using an oxide semiconductor, an oxide semiconductor layer which is dehydrated or dehydrogenated by a heat treatment is used as an active layer, a crystal region including nanocrystals is included in a superficial portion in the channel formation region, and the rest portion is amorphous or is formed of a mixture of amorphousness/non-crystals and microcrystals, where an amorphous region is dotted with microcrystals. By using an oxide semiconductor layer having such a structure, a change to an n-type caused by entry of moisture or elimination of oxygen to or from the superficial portion and generation of a parasitic channel can be prevented and a contact resistance with a source and drain electrodes can be reduced.
    Type: Application
    Filed: October 4, 2010
    Publication date: April 14, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Masayuki Sakakura, Ryosuke Watanabe, Junichiro Sakata, Kengo Akimoto, Akiharu Miyanaga, Takuya Hirohashi, Hideyuki Kishida
  • Publication number: 20110075756
    Abstract: A transmitter includes an OFDM symbol generator for generating an effective symbol including a plurality of sub-carriers orthogonal to each other in frequency and sequentially generating an OFDM symbol in which a signal in a first period from a first end of the effective symbol is added to a second end of the effective symbol as a guard interval, and a convolution filter for performing an convolution operation on data strings at a plurality of sampling points of the OFDM symbol, wherein when the convolution filter performs a convolution operation on the first data strings including a data string at the first end of the effective symbol, the convolution filter performs the convolution operation on the first data strings in which a data string at the second end of the effective symbol is cyclically added to a data string at the first end.
    Type: Application
    Filed: September 27, 2010
    Publication date: March 31, 2011
    Applicant: Fujitsu Semiconductor Limited
    Inventor: Ryosuke WATANABE
  • Publication number: 20110068335
    Abstract: It is an object to provide a highly reliable semiconductor device with good electrical characteristics and a display device including the semiconductor device as a switching element. In a transistor including an oxide semiconductor layer, a needle crystal group provided on at least one surface side of the oxide semiconductor layer grows in a c-axis direction perpendicular to the surface and includes an a-b plane parallel to the surface, and a portion except for the needle crystal group is an amorphous region or a region in which amorphousness and microcrystals are mixed. Accordingly, a highly reliable semiconductor device with good electrical characteristics can be formed.
    Type: Application
    Filed: September 22, 2010
    Publication date: March 24, 2011
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei YAMAZAKI, Masayuki SAKAKURA, Ryosuke WATANABE, Junichiro SAKATA, Kengo AKIMOTO, Akiharu MIYANAGA, Takuya HIROHASHI, Hideyuki KISHIDA
  • Publication number: 20110062436
    Abstract: To provide a transistor having a favorable electric characteristics and high reliability and a display device including the transistor. The transistor is a bottom-gate transistor formed using an oxide semiconductor for a channel region. An oxide semiconductor layer subjected to dehydration or dehydrogenation through heat treatment is used as an active layer. The active layer includes a first region of a superficial portion microcrystallized and a second region of the rest portion. By using the oxide semiconductor layer having such a structure, a change to an n-type, which is attributed to entry of moisture to the superficial portion or elimination of oxygen from the superficial portion, and generation of a parasitic channel can be suppressed. In addition, contact resistance between the oxide semiconductor layer and source and drain electrodes can be reduced.
    Type: Application
    Filed: September 13, 2010
    Publication date: March 17, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Masayuki SAKAKURA, Ryosuke WATANABE, Junichiro SAKATA, Kengo AKIMOTO, Akiharu MIYANAGA, Takuya HIROHASHI, Hideyuki KISHIDA