Abstract: A semiconductor device includes an N-type semiconductor substrate comprising silicon, an N-type low-concentration impurity layer that is in contact with the upper surface of the N-type semiconductor substrate, a metal layer that is in contact with the entire lower surface of the N-type semiconductor substrate and has a thickness of at least 20 ?m, and first and second vertical MOS transistors formed in the low-concentration impurity layer. The ratio of the thickness of the metal layer to the thickness of a semiconductor layer containing the N-type semiconductor substrate and the low-concentration impurity layer is greater than 0.27. The semiconductor device further includes a support comprising a ceramic material and bonded to the entire lower surface of the metal layer only via a bonding layer.

Abstract: A semiconductor device includes: a semiconductor (10 ?m?tsi?30 ?m); a metal layer (30 ?m?tag?60 ?m) comprising Ag; a metal layer (10 ?m?tni?35 ?m) comprising Ni; and transistors. The transistors include a source electrode and a gate electrode on the semiconductor layer. The metal layer functions as a common drain region for the transistors. The ratio of the lengths of the longer side and the shorter side of the semiconductor layer is at most 1.73. The ratio of the surface area and the perimeter length of each electrode included in the source electrode is at most 0.127. The cumulative surface area of the source electrode and the gate electrode is at most 2.61 mm2. The length of the shorter side of the source electrode is at most 0.3 mm, and 702<2.33×tsi+10.5×tag+8.90×tni<943 is satisfied.

Abstract: A semiconductor device includes an N-type semiconductor substrate comprising silicon, an N-type low-concentration impurity layer that is in contact with the upper surface of the N-type semiconductor substrate, a metal layer that is in contact with the entire lower surface of the N-type semiconductor substrate and has a thickness of at least 20 ?m, and first and second vertical MOS transistors formed in the low-concentration impurity layer. The ratio of the thickness of the metal layer to the thickness of a semiconductor layer containing the N-type semiconductor substrate and the low-concentration impurity layer is greater than 0.27. The semiconductor device further includes a support comprising a ceramic material and bonded to the entire lower surface of the metal layer only via a bonding layer.

Abstract: A semiconductor device includes: a semiconductor (10 ?m?tsi?30 ?m); a metal layer (30 ?m?tag?60 ?m) comprising Ag; a metal layer (10 ?m?tni?35 ?m) comprising Ni; and transistors. The transistors include a source electrode and a gate electrode on the semiconductor layer. The metal layer functions as a common drain region for the transistors. The ratio of the lengths of the longer side and the shorter side of the semiconductor layer is at most 1.73. The ratio of the surface area and the perimeter length of each electrode included in the source electrode is at most 0.127. The cumulative surface area of the source electrode and the gate electrode is at most 2.61 mm2. The length of the shorter side of the source electrode is at most 0.3 mm, and 702<2.33×tsi+10.5×tag+8.90×tni<943 is satisfied.

Abstract: A semiconductor device includes an N-type semiconductor substrate comprising silicon, an N-type low-concentration impurity layer that is in contact with the upper surface of the N-type semiconductor substrate, a metal layer that is in contact with the entire lower surface of the N-type semiconductor substrate and has a thickness of at least 20 ?m, and first and second vertical MOS transistors formed in the low-concentration impurity layer. The ratio of the thickness of the metal layer to the thickness of a semiconductor layer containing the N-type semiconductor substrate and the low-concentration impurity layer is greater than 0.27. The semiconductor device further includes a support comprising a ceramic material and bonded to the entire lower surface of the metal layer only via a bonding layer.

Abstract: A semiconductor device includes a first gate electrode, a plurality of first source electrodes, a second gate electrode, and a plurality of second source electrodes. The first gate electrode is arranged with no other electrode between the first gate electrode and a first short side of the semiconductor substrate. The plurality of first source electrodes include a plurality of approximately rectangular first source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate. The second gate electrode is arranged with no other electrode between the second gate electrode and a second short side of the semiconductor substrate. The plurality of second source electrodes include a plurality of approximately rectangular second source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate.

Abstract: A semiconductor device includes a first gate electrode, a plurality of first source electrodes, a second gate electrode, and a plurality of second source electrodes. The first gate electrode is arranged with no other electrode between the first gate electrode and a first short side of the semiconductor substrate. The plurality of first source electrodes include a plurality of approximately rectangular first source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate. The second gate electrode is arranged with no other electrode between the second gate electrode and a second short side of the semiconductor substrate. The plurality of second source electrodes include a plurality of approximately rectangular second source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate.

Abstract: A semiconductor device includes a first gate electrode, a plurality of first source electrodes, a second gate electrode, and a plurality of second source electrodes. The first gate electrode is arranged with no other electrode between the first gate electrode and a first short side of the semiconductor substrate. The plurality of first source electrodes include a plurality of approximately rectangular first source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate. The second gate electrode is arranged with no other electrode between the second gate electrode and a second short side of the semiconductor substrate. The plurality of second source electrodes include a plurality of approximately rectangular second source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate.

Abstract: A semiconductor device includes an N-type semiconductor substrate comprising silicon, an N-type low-concentration impurity layer that is in contact with the upper surface of the N-type semiconductor substrate, a metal layer that is in contact with the entire lower surface of the N-type semiconductor substrate and has a thickness of at least 20 ?m, and first and second vertical MOS transistors formed in the low-concentration impurity layer. The ratio of the thickness of the metal layer to the thickness of a semiconductor layer containing the N-type semiconductor substrate and the low-concentration impurity layer is greater than 0.27. The semiconductor device further includes a support comprising a ceramic material and bonded to the entire lower surface of the metal layer only via a bonding layer.

Abstract: A semiconductor device includes a first gate electrode, a plurality of first source electrodes, a second gate electrode, and a plurality of second source electrodes. The first gate electrode is arranged with no other electrode between the first gate electrode and a first short side of the semiconductor substrate. The plurality of first source electrodes include a plurality of approximately rectangular first source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate. The second gate electrode is arranged with no other electrode between the second gate electrode and a second short side of the semiconductor substrate. The plurality of second source electrodes include a plurality of approximately rectangular second source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate.

Abstract: A semiconductor device includes a first gate electrode, a plurality of first source electrodes, a second gate electrode, and a plurality of second source electrodes. The first gate electrode is arranged with no other electrode between the first gate electrode and a first short side of the semiconductor substrate. The plurality of first source electrodes include a plurality of approximately rectangular first source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate. The second gate electrode is arranged with no other electrode between the second gate electrode and a second short side of the semiconductor substrate. The plurality of second source electrodes include a plurality of approximately rectangular second source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate.

Abstract: A semiconductor device includes a first gate electrode, a plurality of first source electrodes, a second gate electrode, and a plurality of second source electrodes. The first gate electrode is arranged with no other electrode between the first gate electrode and a first short side of the semiconductor substrate. The plurality of first source electrodes include a plurality of approximately rectangular first source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate. The second gate electrode is arranged with no other electrode between the second gate electrode and a second short side of the semiconductor substrate. The plurality of second source electrodes include a plurality of approximately rectangular second source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate.

Abstract: The present invention improves luminous efficiency of a nitride semiconductor light-emitting element. In the nitride semiconductor light-emitting element, a non-polar or semi-polar Alx2Iny2Gaz2N layer having a thickness of t1 is interposed between the Alx1Iny1Gaz1N layer included in the p-type nitride semiconductor layer and the active layer (0<x2?1, 0?y2<1, 0<z2<1, x2+y2+z2=1). The Alx2Iny2Gaz2N layer has first and second interfaces located close to or in contact with the active layer and the Alx1Iny1Gaz1N layer, respectively. The Alx2Iny2Gaz2N layer has a hydrogen concentration distribution along its thickness direction in the inside thereof in such a manner that the hydrogen concentration is increased from the first interface to a thickness t2 (t2<t1), reaches a peak at the thickness t2, and is decreased from the thickness t2 to the second interface. Magnesium contained in the Alx1Iny1Gaz1N layer is prevented from being diffused into the active layer to improve the luminous efficiency.

Abstract: Provided is a nitride semiconductor light-emitting diode in which efficiency in a low current density is prevented from being decreased. The nitride semiconductor light-emitting diode comprises a second n-type nitride semiconductor layer. An active layer has a principal surface of an m-plane having an off angle of not less than 0 degrees and not more than 15 degrees. Either of the following requirement (A) and (B) is satisfied; (A) the second n-type nitride semiconductor layer has a donor impurity concentration of not less than 3.0×1017 cm?3 and less than 1.5×1018 cm?3, and the p-type nitride semiconductor has an acceptor impurity concentration of not less than 5.0×1017 cm?3 and less than 1.0×1018 cm?3, or (B) the second n-type nitride semiconductor layer has a donor impurity concentration of not less than 3.0×1017 cm?3 and not more than 2.5×1018 cm?3, and the p-type nitride semiconductor has an acceptor impurity concentration of not less than 1.0×1018 cm?3.

Abstract: A nitride-based semiconductor light-emitting device includes: a nitride-based semiconductor multilayer structure including a p-type semiconductor region having an m-plane as a growing plane; and an Ag electrode provided so as to be in contact with the growing plane of the p-type semiconductor region, wherein the Ag electrode has a thickness in a range of not less than 200 nm and not more than 1,000 nm; an integral intensity ratio of an X-ray intensity of a (111) plane on the growing plane of the Ag electrode to that of a (200) plane is in a range of not less than 20 and not more than 100; and the Ag electrode has a reflectance of not less than 70%.

Abstract: A nitride semiconductor light-emitting element includes: n-side and p-side electrodes; n-type and p-type nitride semiconductor layers; and an active layer arranged between the n- and p-type nitride semiconductor layers. The p-type nitride semiconductor layer has a projection having a height of 30 nm to 50 nm. The projection is formed of a p-type nitride semiconductor including magnesium and silicon. The p-type nitride semiconductor has a silicon concentration of 1.0×1017 cm?3 to 6.0×1017 cm?3. The projection projects from the active layer toward the p-side electrode. On a plan view of the nitride semiconductor light-emitting element, the p-side electrode overlaps with the projection. The projection includes a dislocation. The projection is surrounded with a flat surface which is formed of the p-type nitride semiconductor. And the projection has a higher dislocation density than the flat surface.

Abstract: In a gallium nitride based compound semiconductor light-emitting element including an active layer, the active layer includes a well layer 104 and a barrier layer 103, each of which is a semiconductor layer of which the growing plane is an m plane. The well layer 104 has a lower surface and an upper surface and has an In composition distribution in which the composition of In changes according to a distance from the lower surface in a thickness direction of the well layer 104. The In composition of the well layer 104 becomes a local minimum at a level that is defined by a certain distance from the lower surface and that portion of the well layer 104 where the In composition becomes the local minimum runs parallel to the lower surface.

Abstract: The present invention improves luminous efficiency of a nitride semiconductor light-emitting element. In the nitride semiconductor light-emitting element, a non-polar or semi-polar Alx2Iny2Gaz2N layer having a thickness of t1 is interposed between the Alx1Iny1Gaz1N layer included in the p-type nitride semiconductor layer and the active layer (0<x2?1, 0?y2<1, 0<z2<1, x2+y2+z2=1). The Alx2Iny2Gaz2N layer has first and second interfaces located close to or in contact with the active layer and the Alx1Iny1Gaz1N layer, respectively. The Alx2Iny2Gaz2N layer has a hydrogen concentration distribution along its thickness direction in the inside thereof in such a manner that the hydrogen concentration is increased from the first interface to a thickness t2 (t2<t1), reaches a peak at the thickness t2, and is decreased from the thickness t2 to the second interface. Magnesium contained in the Alx1Iny1Gaz1N layer is prevented from being diffused into the active layer to improve the luminous efficiency.

Abstract: A nitride-based semiconductor element according to an embodiment of the present disclosure includes: a p-type contact layer, of which the growing plane is an m plane; and an electrode which is arranged on the growing plane of the p-type contact layer. The p-type contact layer is a GaN-based semiconductor layer which has a thickness of 26 nm to 60 nm and which includes oxygen at a concentration that is equal to or higher than Mg concentration of the p-type contact layer. In the p-type contact layer, the number of Ga vacancies is larger than the number of N vacancies.

Abstract: A nitride semiconductor light-emitting element uses a non-polar plane as its growing plane. A GaN/InGaN multi-quantum well active layer includes an Si-doped layer which is arranged in an InyGa1-yN (where 0<y<1) well layer, between the InyGa1-yN (where 0<y<1) well layer and a GaN barrier layer, or in a region of the GaN barrier layer that is located closer to the InyGa1-yN (where 0<y<1) well layer. A concentration of Si at one interface of the GaN barrier layer on a growing direction side is either zero or lower than a concentration of Si in the Si-doped layer.