Abstract: There is disclosed a semiconductor integrated circuit device comprising a memory cell array including a memory cell having a ferroelectric capacitor having first and second electrodes. A first bit line is electrically connected to the first electrode. A first potential generation circuit supplies a first potential to the second electrode to apply a voltage which drops at a first rate of change with a rise of temperature to the ferroelectric capacitor. A sense amplifier amplifies a potential difference between the first bit line and a second bit line complementary to the first bit line.

Abstract: A semiconductor memory device includes a memory cell array, a sense amplifier, and a voltage generator. The memory cell array has a plurality of memory cells. Each of the memory cells is written with “0” or “1” as reference data after “0” or “1” as cell data has been read out from the memory cell. The sense amplifier compares and amplifies the reference data and the cell data read from a memory cell. The voltage generator keeps constant rate of change with time of at least one potential supplied for a read operation for the time interval from readout of the cell data is started until completion of readout of the reference data.

Abstract: A semiconductor storage device comprises first and second memory cells, each connected to the first pair of word line and bit line and a second pair of word line and bit line, a sense amplifier connected between the first and second bit lines, a first capacitor whose storage electrode being connected to the first bit line, a second capacitor whose storage electrode being connected to the second bit line, first and second wires respectively connected to the first and second plate electrodes of the first and second capacitors, wherein the first and second bit lines are in a complementary relation, and when “0” is read to the first bit line, the first capacitor has an operation to increase a potential of the first plate electrode through the first wire before the sense amplifier operates.

Abstract: Potential of a word line connected to any selected one of memory cells is lowered and potential of word lines connected to non-selected memory cells are raised. The potential of the plate line is raised and lowered. The potential of the bit line is raised and lowered. After this, reading data from the memory cells after potential raising and lowering of the plate line and potential raising and lowering of the bit line have been alternately performed at least one time, thereby to determine attenuation of polarization in the ferroelectric capacitor.

Abstract: A semiconductor integrated circuit device includes first and second bit lines (BLs), first and second plate lines (PLs), a first series connected TC unit type structure connected between the first BL and the first PL, a second series connected TC unit type structure connected between the second BL and the second PL, a PL potential control circuit, and a BL potential control circuit. The PL potential control circuit controls a potential of the first PL from a first potential to a second potential and a potential of the second PL from the first potential to a third potential, when the first series connected TC unit type structure is selected. The BL potential control circuit controls a potential of the second BL to the third potential, after charges are transferred from the first series connected TC unit type structure to the first BL.

Abstract: A dummy capacitor drive potential VDC is given to one electrode of a dummy capacitor, and a reference potential for determining a data value of a memory cell is generated in the other electrode thereof. A potential generator circuit for generating the potential VDC is composed of a BGR circuit outputting a potential VBGRTEMP having temperature dependency, and resistors R3 and R4, which are series-connected between an output terminal of the BGR circuit and a ground point. The potential VDC is output from a connection point of the resistors R3 and R4. Temperature dependency of the potential VDC is adjusted based on a resistance ratio of resistors R1-1, R1-2 and R2, and the absolute value is adjusted based on a resistance ratio of resistors R3 and R4.

Abstract: A ferroelectric memory comprising a plurality of memory cells each including a ferroelectric capacitor and a switch transistor, and operating in a test mode in which, after polarized data is written into the memory cell by applying a first electric potential difference between both electrodes of ferroelectric capacitors of the plurality of memory cells, and before reading of the polarized data from the memory cells is carried out, a second electric potential difference smaller than the first electric potential difference is applied between both the electrodes of the ferroelectric capacitors in a direction opposite to that at the time of writing the polarized data.

Abstract: A semiconductor device comprises a memory cell array, bit line, /bit line complementary to the bit line, reference voltage generating circuit and sense amplifier. The bit line is connected to the memory cells and applied with a voltage read from each memory cell of the memory cell array. The /bit line is supplied with a reference voltage. The reference voltage generating circuit generates the reference voltage that has temperature dependence for compensating a change in the voltage, read to the bit line, due to temperature. The reference voltage generating circuit controls the reference voltage such that the reference voltage assumes a midpoint of trails of a signal value distribution indicative of “0” data and a signal value distribution indicative of “1” data. The sense amplifier compares the voltage, read to the bit line, with the reference voltage supplied to the /bit line, and amplifies the difference therebetween.

Abstract: There is disclosed a semiconductor integrated circuit device comprising a memory cell array including a memory cell having a ferroelectric capacitor having first and second electrodes. A first bit line is electrically connected to the first electrode. A first potential generation circuit supplies a first potential to the second electrode to apply a voltage which drops at a first rate of change with a rise of temperature to the ferroelectric capacitor. A sense amplifier amplifies a potential difference between the first bit line and a second bit line complementary to the first bit line.

Abstract: A semiconductor device comprises a memory cell array, bit line, /bit line complementary to the bit line, reference voltage generating circuit and sense amplifier. The bit line is connected to the memory cells and applied with a voltage read from each memory cell of the memory cell array. The /bit line is supplied with a reference voltage. The reference voltage generating circuit generates the reference voltage that has temperature dependence for compensating a change in the voltage, read to the bit line, due to temperature. The reference voltage generating circuit controls the reference voltage such that the reference voltage assumes a midpoint of trails of a signal value distribution indicative of “0” data and a signal value distribution indicative of “1” data. The sense amplifier compares the voltage, read to the bit line, with the reference voltage supplied to the /bit line, and amplifies the difference therebetween.

Abstract: A phase-change memory device includes memory cells, a memory cell array, a first electrode layer, a word line, and a bit line. The memory cell includes a phase-change layer formed on a semiconductor substrate. The memory cell array has the memory cells arranged in a matrix. The phase change layer includes first regions which contact the semiconductor substrate in units of memory cells and a second region which connects the first regions arranged in a same column. The first electrode layer is formed on the second region. A contact area of each first region and the semiconductor substrate is smaller than a contact area of the second region and the first electrode layer. The bit line is electrically connected to the first electrode layer. The bit line is connects in common the phase-change layers of the memory cells arranged in the same column.

Abstract: A semiconductor integrated circuit device includes first and second bit lines (BLs), first and second plate lines (PLs), a first series connected TC unit type structure connected between the first BL and the first PL, a second series connected TC unit type structure connected between the second BL and the second PL, a PL potential control circuit, and a BL potential control circuit. The PL potential control circuit controls a potential of the first PL from a first potential to a second potential and a potential of the second PL from the first potential to a third potential, when the first series connected TC unit type structure is selected. The BL potential control circuit controls a potential of the second BL to the third potential, after charges are transferred from the first series connected TC unit type structure to the first BL.

Abstract: A ferroelectric memory comprising a plurality of memory cells each including a ferroelectric capacitor and a switch transistor, and operating in a test mode in which, after polarized data is written into the memory cell by applying a first electric potential difference between both electrodes of ferroelectric capacitors of the plurality of memory cells, and before reading of the polarized data from the memory cells is carried out, a second electric potential difference smaller than the first electric potential difference is applied between both the electrodes of the ferroelectric capacitors in a direction opposite to that at the time of writing the polarized data.

Abstract: A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier. A value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.

Abstract: A semiconductor device comprises a memory cell array, bit line, /bit line complementary to the bit line, reference voltage generating circuit and sense amplifier. The bit line is connected to the memory cells and applied with a voltage read from each memory cell of the memory cell array. The /bit line is supplied with a reference voltage. The reference voltage generating circuit generates the reference voltage that has temperature dependence for compensating a change in the voltage, read to the bit line, due to temperature. The reference voltage generating circuit controls the reference voltage such that the reference voltage assumes a midpoint of trails of a signal value distribution indicative of “0” data and a signal value distribution indicative of “1” data. The sense amplifier compares the voltage, read to the bit line, with the reference voltage supplied to the /bit line, and amplifies the difference therebetween.

Abstract: A chain type ferroelectric random access memory has a memory cell unit comprising ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier, and that a value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.

Abstract: A chain type ferroelectric random access memory has a memory cell unit comprising ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier, and that a value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.

Abstract: A chain type ferroelectric random access memory has a memory cell unit comprising ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier, and that a value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.

Abstract: A chain type ferroelectric random access memory has a memory cell unit comprising ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier, and that a value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.

Abstract: Potential of a word line connected to any selected one of memory cells is lowered and potential of word lines connected to non-selected memory cells are raised. The potential of the plate line is raised and lowered. The potential of the bit line is raised and lowered. After this, reading data from the memory cells after potential raising and lowering of the plate line and potential raising and lowering of the bit line have been alternately performed at least one time, thereby to determine attenuation of polarization in the ferroelectric capacitor.