Abstract: A chain type ferroelectric random access memory has a memory cell unit comprising ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier, and that a value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.

Abstract: A semiconductor memory device reads data corresponding to charges stored in a capacitor in a memory cell and rewrites the data. This semiconductor memory device removes charges stored in the capacitor in the memory cell to a bit line or absorbs charges stored in the bit line into the capacitor in the memory cell, thereby generating a potential difference between the bit line pair. This potential difference is sensed by a sense amplifier and rewritten. Before the sense amplifier is operated, the potential difference is generated between the bit line pair. The parasitic capacitances of the bit line pair during operation of the sense amplifier are substantially equalized, and in this state, the potential difference is sensed.

Abstract: A dummy cell is provided in every column and consists of a dummy capacitor and two transistors. When the charge of the ferroelectric capacitor is released to one of a bit line pair, a first dummy word line is selected and charge of the dummy capacitor is released to the other of the bit line pair by way of one of the two transistors. When the charge of the ferroelectric capacitor is released to the other of the bit line pair, a second dummy word line is selected and the charge of the dummy capacitor is released to one of the bit line pair by way of the other one of the two transistors. When either one of the first and second dummy word lines is selected the dummy plate driver supplies a clock signal to the dummy capacitor.

Abstract: A semiconductor memory device reads data corresponding to charges stored in a capacitor in a memory cell and rewrites the data. This semiconductor memory device removes charges stored in the capacitor in the memory cell to a bit line or absorbs charges stored in the bit line into the capacitor in the memory cell, thereby generating a potential difference between the bit line pair. This potential difference is sensed by a sense amplifier and rewritten. Before the sense amplifier is operated, the potential difference is generated between the bit line pair. The parasitic capacitances of the bit line pair during operation of the sense amplifier are substantially equalized, and in this state, the potential difference is sensed.

Abstract: A sense amplifier is connected between memory cell arrays, a re-writing register is arranged adjacent to the sense amplifier, first transfer gates are disposed between the sense amplifier and the memory cell arrays, second transfer gates are provided between bit lines of the memory cell arrays and global bit lines, and a gate control circuit for controlling the transfer gates is provided. When readout data is written into the register, the node of the sense amplifier is electrically separated from the bit lines and global bit lines.

Abstract: A sense amplifier is connected between memory cell arrays, a re-writing register is arranged in position adjacent to the sense amplifier, transfer gates are disposed between the sense amplifier and the memory cell arrays, transfer gates are provided between bit lines of the memory cell arrays and global bit lines, and a gate control circuit for controlling the transfer gates is provided. When readout data is written into the register, the node of the sense amplifier is electrically separated from the bit lines and global bit lines.

Abstract: A semiconductor memory device includes a series of memory cells, a series of bit lines respectively connected to the memory cells, a series of sense amplifiers, connected to corresponding bit line groups including predetermined number of bit lines of the series of bit lines, for reading out data of memory cells connected to bit lines of the bit line group, the bit line groups including at least adjacent first and second bit line groups, at least first and second transistors allocated between the bit lines and the sense amplifiers and having gates, for selectively connecting the bit lines and the sense amplifiers, and a series of control signal lines commonly connected to the first transistors connected to the first bit line groups and the second transistors connected to the second bit line groups, such that the first transistors connected to the first bit line groups are regularly arranged in one direction, and second transistors connected to the second bit line groups adjacent to the first bit line groups ar