Abstract: A polymer membrane for water treatment, characterized in comprising a hollow fiber membrane having a self-supporting design composed of the substantially single principal structural material, with an outer diameter of 3.6 mm to 10 mm and a ratio of outer diameter to thickness, SDR, of 3.6 to 34.

Abstract: A polymer membrane for water treatment, characterized in comprising a hollow fiber membrane having a self-supporting design composed of the substantially single principal structural material, with an outer diameter of 3.6 mm to 10 mm and a ratio of outer diameter to thickness, SDR, of 3.6 to 34.

Abstract: A polymer membrane for water treatment composed of a vinyl chloride copolymer comprising a vinyl chloride monomer and a hydrophilic monomer.

Abstract: The present invention provides a process for producing an oriented thermoplastic polyester resin sheet which is excellent in tensile strength, tencile modulas and heat resistance, and a light laminate-molded body using the same, which has a low linear expansion coefficient and is excellent in impact resistance, durability, easiness of handling, productivity, and others. A process for producing an oriented thermoplastic polyester resin sheet, which includes: pultrusion-drawing a thermoplastic polyester resin sheet in an amorphous state at a temperature from the glass transition temperature of the thermoplastic polyester resin ?20° C. to the glass transition temperature of the thermoplastic polyester resin +20° C.; and then drawing the resultant uniaxially at a temperature higher than the temperature for the pultrusion-drawing. A laminate-molded body, wherein a thermoplastic resin layer is laminated on each of the surfaces of the resultant oriented thermoplastic polyester resin sheet.

Abstract: A polymer membrane for water treatment, characterized in comprising a hollow fiber membrane having a self-supporting design composed of the substantially single principal structural material, with an outer diameter of 3.6 mm to 10 mm and a ratio of outer diameter to thickness, SDR, of 3.6 to 34.

Abstract: A polymer membrane for water treatment composed of a vinyl chloride copolymer comprising a vinyl chloride monomer and a hydrophilic monomer.

Abstract: A polymer membrane for water treatment contained a chlorinated vinyl chloride resin with a chlorine content of 58 to 73.2%. According to the present invention, it is possible to provide polymer membranes for water treatment that, along with being able to achieve sufficient filtration capacity and water permeability, have extremely high strength.

Abstract: A polymer membrane for water treatment contained a chlorinated vinyl chloride resin with a chlorine content of 58 to 73.2%. According to the present invention, it is possible to provide polymer membranes for water treatment that, along with being able to achieve sufficient filtration capacity and water permeability, have extremely high strength.

Abstract: The present invention provides a process for producing an oriented thermoplastic polyester resin sheet which is excellent in tensile strength, tencile modulas and heat resistance, and a light laminate-molded body using the same, which has a low linear expansion coefficient and is excellent in impact resistance, durability, easiness of handling, productivity, and others. A process for producing an oriented thermoplastic polyester resin sheet, which includes: pultrusion-drawing a thermoplastic polyester resin sheet in an amorphous state at a temperature from the glass transition temperature of the thermoplastic polyester resin?20° C. to the glass transition temperature of the thermoplastic polyester resin+20° C.; and then drawing the resultant uniaxially at a temperature higher than the temperature for the pultrusion-drawing. A laminate-molded body, wherein a thermoplastic resin layer is laminated on each of the surfaces of the resultant oriented thermoplastic polyester resin sheet.

Abstract: A composite material comprising a core layer comprising filler and synthetic resin and containing the filler having a weight 0.7 times or more the product of volume of the core layer and bulk density of the filler; and a surface layer comprising a thermosetting resin reinforced by long fibers extending parallel in a longitudinal direction thereof, the surface layer being laminated on the core layer to cover at least one surface of the core layer with respect to a thickness direction thereof.

Abstract: A semiconductor integrated circuit device includes a first conductor formed on a main surface of a semiconductor substrate with an insulating film therebetween, and a second conductor formed with an insulating film therebetween so as to be placed near one side of the first conductor and to have its one end extended over a top surface of the one side of the first conductor. The semiconductor integrated circuit device further includes an impurity diffusion layer at the main surface of the semiconductor substrate under a region where first and second conductors are close to each other. In accordance with this structure, higher degree of integration of a memory cell can be readily achieved by a relatively simple manufacturing process.

Abstract: A semiconductor memory device comprises a dynamic memory cell array, a static memory cell array, a plurality of word lines, a plurality of DRAM bit line pairs and a plurality of SRAM bit line pairs. The dynamic memory cell array comprises a plurality of dynamic memory cells arranged in the shape of a matrix. The static memory cell array is arranged adjacent to the dynamic memory cell array. The static memory cell array includes the static memory cells arranged in the shape of a matrix. A plurality of word lines are arranged in a plurality of rows. Each word line is connected to the dynamic and static memory cells arranged in the corresponding rows. A plurality of DRAM bit line pairs are arranged in a plurality of columns. Each DRAM bit line pair is connected to the dynamic memory cells. A plurality of SRAM bit line pairs are arranged in the other plurality of columns. Each SRAM bit line pair is connected to the static memory cells arranged in the corresponding columns.

Abstract: A non-volatile SRAM cell (MC) includes floating gate type transistors (1a, 1b) arranged between power supply nodes (4a, 4b) and storage nodes (A, B), and flip-flops (2a, 2b) holding signal potentials of the storage nodes. The floating gate type transistor has a drain connected to the power supply node, and a control gate connected to a control electrode node (5). Voltages are applied independently to the drains and the control gate of the floating gate type transistor, whereby a large amount of hot electrons are efficiently generated by avalanche breakdown and are accelerated to be injected into the floating gate. Removal of electrons is achieved by the voltages applied to the control gate and the drain. In the non-volatile SRAM cell utilizing the floating gate type transistor, injection and removal of electrons with respect to the floating gate are efficiently performed to change a threshold voltage for reliably storing information in a non-volatile manner.

Abstract: Obtained is a semiconductor device which can effectively prevent a gate oxide film from deterioration or breaking caused by plasma charged particles which are accumulated in a wiring layer in plasma etching thereof, even if an antenna ratio is increased. In this semiconductor device, an impurity diffusion layer forming a resistor and a diode is interposed between a gate electrode layer of a field-effect transistor of an internal circuit other than an initial input stage circuit and a first wiring layer for transmitting a circuit signal to the gate electrode layer. Thus, plasma charged particles which are accumulated in the first wiring layer in plasma etching thereof are absorbed by the impurity diffusion layer, whereby no surge voltage is applied to the gate electrode layer which is connected with the first wiring layer. Thus, the gate oxide film which is positioned under the gate electrode layer is prevented from breaking or deterioration.

Abstract: An input circuit 200 includes first to fourth switching transistors T1-T4 to be controlled by clock signals CLK and /CLK, and two latch circuits 202 and 204. In response to a rising edge of the clock signal, switching transistor T1 is turned on, and latch circuit 202 takes in data. In response to a falling edge of clock signal CLK, switching transistor T3 is turned on, and latch circuit 204 takes in the data. Since input and output of the data are performed at both the rising edge and the falling edge of the clock signal, the operation can be performed at double the frequency.

Abstract: A semiconductor memory device comprises a dynamic memory cell array, a static memory cell array, a plurality of word lines, a plurality of DRAM bit line pairs and a plurality of SRAM bit line pairs. The dynamic memory cell array comprises a plurality of dynamic memory cells arranged in the shape of a matrix. The static memory cell array is arranged adjacent to the dynamic memory cell array. The static memory cell array includes the static memory cells arranged in the shape of a matrix. A plurality of word lines are arranged in a plurality of rows. Each word line is connected to the dynamic and static memory cells arranged in the corresponding rows. A plurality of DRAM bit line pairs are arranged in a plurality of columns. Each DRAM bit line pair is connected to the dynamic memory cells. A plurality of SRAM bit line pairs are arranged in the other plurality of columns. Each SRAM bit line pair is connected to the static memory cells arranged in the corresponding columns.

Abstract: A semiconductor memory device comprising a memory cell array, a row decoder, an input/output register train, a burst counter, an input/output bus, a refresh counter and a multiplexer. The memory cell array includes a plurality of word lines, a plurality of bit line pairs and a plurality of memory cells. The input/output register train has a plurality of registers corresponding to the bit line pairs. Each of the registers is connected to the corresponding bit line pair. The input/output bus inputs and outputs data to and from the register train in response to a signal from the burst counter. The multiplexer supplies the row decoder with an external address signal as an internal address signal. After data is transferred from any bit line pair to the register or before data is transferred from any register to the bit line pair, the multiplexer supplies the row decoder with a refresh address signal from the refresh counter in place of the external address signal.

Abstract: A non-volatile SRAM cell (MC) includes floating gate type transistors (1a, 1b) arranged between power supply nodes (4a, 4b) and storage nodes (A, B), and flip-flops (2a, 2b) holding signal potentials of the storage nodes. The floating gate type transistor has a drain connected to the power supply node, and a control gate connected to a control electrode node (5). Voltages are applied independently to the drains and the control gate of the floating gate type transistor, whereby a large amount of hot electrons are efficiently generated by avalanche breakdown and are accelerated to be injected into the floating gate. Removal of electrons is achieved by the voltages applied to the control gate and the drain. In the non-volatile SRAM cell utilizing the floating gate type transistor, injection and removal of electrons with respect to the floating gate are efficiently performed to change a threshold voltage for reliably storing information in a non-volatile manner.

Abstract: A semiconductor integrated circuit device includes a first conductor formed on a main-surface of a semiconductor substrate with an insulating film therebetween, and a second conductor formed with an insulating film therebetween so as to be placed near one side of the first conductor and to have its one end extended over a top surface of the one side of the first conductor. The semiconductor integrated circuit device further includes an impurity diffusion layer at the main surface of the semiconductor substrate under a region where first and second conductors are close to each other. In accordance with this structure, higher degree of integration of a memory cell can be readily achieved by a relatively simple manufacturing process.

Abstract: A semiconductor memory device includes an array of memory cells arranged in rows and columns; a plurality of word lines connected to the rows of the memory cells; a plurality of bit lines connected to the columns of the memory cells; word line selection means; bit line selection means; and equalizing means for equalizing the bit line to a desired voltage level in response to an address signal, and for terminating the equalization in response to change in a signal on a word line according to change in the address signal.