Abstract: Cross talk among wirings formed in an interposer is reduced while increase in a parasitic capacitance among the wirings formed in the interposer is suppressed. A semiconductor device has an interposer including a first wiring layer, a second wiring layer formed above the first wiring layer, and a third wiring layer formed above the second wiring layer. In a plan view, a first signal wiring formed in the first wiring layer and a reference wiring formed in the second wiring layer are distant from each other. Similarly, in a plan view, the reference wiring formed in the second wiring layer and a third signal wiring formed in a third wiring layer are distant from each other.

Abstract: A semiconductor device includes first and second semiconductor components mounted on an interposer mounted on a wiring substrate, and electrically connected to each other via the interposer. Also, a plurality of wiring layers of the interposer include first, second and third wiring layers which are stacked in order from a main surface side to be a reference. In addition, in a first region of the interposer sandwiched between the first semiconductor component and the second semiconductor component, a ratio of a reference potential wiring in the third wiring layer is higher than a ratio of a reference potential wiring in the first wiring layer. Further, in the first region, a ratio of a signal wiring in the first wiring layer is higher than a ratio of a signal wiring in the third wiring layer.

Abstract: To improve signal transmission characteristics of a high frequency signal of 80 GHz or higher. A semiconductor device includes a wiring board having a structure in which a signal via structure and a grounding via structure have mutually overlapping portions in plan view.

Abstract: The present invention provides a semiconductor device realizing suppression of increase in consumption power. A semiconductor device has a signal line, a reception buffer circuit which is coupled to an end of the signal line and to which a signal is supplied from the signal line, and a delay element which is wired-OR coupled to an end of the signal line and shapes waveform of a signal at the end of the signal line.

Abstract: The present invention provides a semiconductor device realizing suppression of increase in consumption power. A semiconductor device has a signal line, a reception buffer circuit which is coupled to an end of the signal line and to which a signal is supplied from the signal line, and a delay element which is wired-OR coupled to an end of the signal line and shapes waveform of a signal at the end of the signal line.

Abstract: To provide an inexpensive semiconductor device capable of suppressing the influence by crosstalk. A semiconductor device includes a signal wiring disposed in an organic interposer, an output circuit which is coupled to a first end of the signal wiring and which sets an impedance so as to generate a reflected wave antiphase to a waveform transmitted to the first end and periodically outputs data, and an input circuit which is coupled to a second end of the signal wiring and sets an impedance so as to generate a reflected wave of the same phase as a waveform transmitted to the second end. An average delay of the signal wiring is set to be 1/integer of 2 or more relative to a half of a cycle of the data. A difference between the maximum and minimum values of a delay of a signal at each of other signal wirings disposed in the organic interposer is set to be not greater than the average delay.

Abstract: To provide an inexpensive semiconductor device capable of suppressing the influence by crosstalk. A semiconductor device includes a signal wiring disposed in an organic interposer, an output circuit which is coupled to a first end of the signal wiring and which sets an impedance so as to generate a reflected wave antiphase to a waveform transmitted to the first end and periodically outputs data, and an input circuit which is coupled to a second end of the signal wiring and sets an impedance so as to generate a reflected wave of the same phase as a waveform transmitted to the second end. An average delay of the signal wiring is set to be 1/integer of 2 or more relative to a half of a cycle of the data. A difference between the maximum and minimum values of a delay of a signal at each of other signal wirings disposed in the organic interposer is set to be not greater than the average delay.

Abstract: A semiconductor device includes first and second semiconductor components mounted on an interposer mounted on a wiring substrate, and electrically connected to each other via the interposer. Also, a plurality of wiring layers of the interposer include first, second and third wiring layers which are stacked in order from a main surface side to be a reference. In addition, in a first region of the interposer sandwiched between the first semiconductor component and the second semiconductor component, a ratio of a reference potential wiring in the third wiring layer is higher than a ratio of a reference potential wiring in the first wiring layer. Further, in the first region, a ratio of a signal wiring in the first wiring layer is higher than a ratio of a signal wiring in the third wiring layer.

Abstract: A semiconductor device includes first and second semiconductor components mounted on an interposer mounted on a wiring substrate, and electrically connected to each other via the interposer. Also, a plurality of wiring layers of the interposer include first, second and third wiring layers which are stacked in order from a main surface side to be a reference. In addition, in a first region of the interposer sandwiched between the first semiconductor component and the second semiconductor component, a ratio of a reference potential wiring in the third wiring layer is higher than a ratio of a reference potential wiring in the first wiring layer. Further, in the first region, a ratio of a signal wiring in the first wiring layer is higher than a ratio of a signal wiring in the third wiring layer.

Abstract: A semiconductor device includes a capacitive element that has frequency dependency that a capacitance value obtained when a second frequency signal that is higher in frequency than a first frequency signal has been applied becomes smaller than a capacitance value obtained when the first frequency signal has been applied and thereby improvement of performance of the semiconductor device is promoted.

Abstract: A semiconductor device includes first and second semiconductor components mounted on an interposer mounted on a wiring substrate, and electrically connected to each other via the interposer. Also, a plurality of wiring layers of the interposer include first, second and third wiring layers which are stacked in order from a main surface side to be a reference. In addition, in a first region of the interposer sandwiched between the first semiconductor component and the second semiconductor component, a ratio of a reference potential wiring in the third wiring layer is higher than a ratio of a reference potential wiring in the first wiring layer. Further, in the first region, a ratio of a signal wiring in the first wiring layer is higher than a ratio of a signal wiring in the third wiring layer.

Abstract: The present invention provides a semiconductor device realizing suppression of increase in consumption power. A semiconductor device has a signal line, a reception buffer circuit which is coupled to an end of the signal line and to which a signal is supplied from the signal line, and a delay element which is wired-OR coupled to an end of the signal line and shapes waveform of a signal at the end of the signal line.

Abstract: To improve noise immunity of a semiconductor device. A wiring substrate of a semiconductor device includes a first wiring layer where a wire is formed to which signals are sent, and a second wiring layer that is mounted adjacent to the upper layer or the lower layer of the first wiring layer. The second wiring layer includes a conductor plane where an aperture section is formed at a position overlapped with a portion of the wire 23 in the thickness direction, and a conductor pattern that is mounted within the aperture section of the conductor plane. The conductor pattern includes a main pattern section (mesh pattern section) that is isolated from the conductor plane, and plural coupling sections that couple the main pattern section and the conductor plane.

Abstract: A semiconductor device includes a semiconductor chip, a plurality of external terminals, and a board. The board includes a first main surface in which a plurality of first electrodes electrically connected to the semiconductor chip are formed, a second main surface in which a plurality of second electrodes electrically connected to the plurality of external terminals are formed, and a plurality of interconnect layers, provided between the first main surface and the second main surface, for forming a plurality of signal paths that electrically connect the first electrode and the second electrode corresponding thereto. The interconnect layer includes a plurality of metal members which are dispersedly disposed at a distance shorter than an electromagnetic wavelength equivalent to a signal band of a signal supplied to the signal path, in the vicinity of a portion in which a structure of an interconnect for forming the signal path is changed.

Abstract: To improve reliability of signal transmission of an interposer which couples between semiconductor chips. A reference potential wiring and a reference potential wiring are provided on both neighboring sides of a signal wiring provided in a first wiring layer of an interposer. Also, a reference potential wiring and a reference potential wiring are provided on both neighboring sides of a signal wiring provided in a second wiring layer of the interposer. Further, the signal wiring and the signal wiring cross each other in plan view. The reference potential wirings of the first wiring layer, and the reference potential wirings of the second wiring layer are coupled to each other at the periphery of their crossing portion.

Abstract: To improve reliability of signal transmission of an interposer which couples between semiconductor chips. A reference potential wiring and a reference potential wiring are provided on both neighboring sides of a signal wiring provided in a first wiring layer of an interposer. Also, a reference potential wiring and a reference potential wiring are provided on both neighboring sides of a signal wiring provided in a second wiring layer of the interposer. Further, the signal wiring and the signal wiring cross each other in plan view. The reference potential wirings of the first wiring layer, and the reference potential wirings of the second wiring layer are coupled to each other at the periphery of their crossing portion.

Abstract: To improve noise immunity of a semiconductor device. A wiring substrate of a semiconductor device includes a first wiring layer where a wire is formed to which signals are sent, and a second wiring layer that is mounted adjacent to the upper layer or the lower layer of the first wiring layer. The second wiring layer includes a conductor plane where an aperture section is formed at a position overlapped with a portion of the wire 23 in the thickness direction, and a conductor pattern that is mounted within the aperture section of the conductor plane. The conductor pattern includes a main pattern section (mesh pattern section) that is isolated from the conductor plane, and plural coupling sections that couple the main pattern section and the conductor plane.

Abstract: To improve noise immunity of a semiconductor device. A wiring substrate of a semiconductor device includes a first wiring layer where a wire is formed to which signals are sent, and a second wiring layer that is mounted adjacent to the upper layer or the lower layer of the first wiring layer. The second wiring layer includes a conductor plane where an aperture section is formed at a position overlapped with a portion of the wire 23 in the thickness direction, and a conductor pattern that is mounted within the aperture section of the conductor plane. The conductor pattern includes a main pattern section (mesh pattern section) that is isolated from the conductor plane, and plural coupling sections that couple the main pattern section and the conductor plane.

Abstract: To improve noise immunity of a semiconductor device. A wiring substrate of a semiconductor device includes a first wiring layer where a wire is formed to which signals are sent, and a second wiring layer that is mounted adjacent to the upper layer or the lower layer of the first wiring layer. The second wiring layer includes a conductor plane where an aperture section is formed at a position overlapped with a portion of the wire 23 in the thickness direction, and a conductor pattern that is mounted within the aperture section of the conductor plane. The conductor pattern includes a main pattern section (mesh pattern section) that is isolated from the conductor plane, and plural coupling sections that couple the main pattern section and the conductor plane.

Abstract: A semiconductor substrate includes a semiconductor chip and an interconnect substrate. The interconnect substrate has an interconnect region between a first main surface formed with plural orderly arranged first and second signal electrodes connected to the semiconductor chip, and a second main surface. The interconnect region has a core substrate, interconnect layers formed on both surfaces thereof, plural first through holes and plural first vias that pass through the interconnect layer on the side of the first main surface for forming impedance matching capacitances. Each first through hole is connected to a first signal interconnect at a position spaced part from the first signal electrode by a first interconnect length and each first via is connected to the second signal interconnect at a position spaced apart from the second signal electrode by a second interconnect length that is substantially equal with the first interconnect length.