Abstract: A semiconductor device includes a semiconductor chip and an interconnect substrate having the semiconductor chip mounted thereon. The interconnect substrate includes a first main surface formed with a plurality of electrodes connected electrically to the semiconductor chip, a second main surface opposing the first main surface, and an interconnect region interposed between the first main surface and the second main surface. The electrodes include a plurality of first electrodes and second electrodes arranged orderly for receiving supply of signals. The first electrodes for signal and the second electrodes are disposed being dispersed in the arrangement thereof, and the interconnect region includes a core substrate, a plurality of interconnect layers formed on both surfaces of the core substrate respectively.

Abstract: An interconnection structure includes: first and second differential signal interconnections provided to transmit a differential signal; and first and second voltage interconnections applied with predetermined voltages. The first voltage interconnection, the first differential signal interconnection, the second differential signal interconnection and the second voltage interconnection are arranged in this order. An interval between the first and second differential signal interconnections is longer than an interval between the first voltage interconnection and the first differential signal interconnection and is longer than an interval between the second differential signal interconnection and the second voltage interconnection.

Abstract: A semiconductor substrate includes a semiconductor chip and an interconnect substrate. The interconnect substrate has an interconnect region between a first main surface formed with plural orderly arranged first and second signal electrodes connected to the semiconductor chip, and a second main surface. The interconnect region has a core substrate, interconnect layers formed on both surfaces thereof, plural first through holes and plural first vias that pass through the interconnect layer on the side of the first main surface for forming impedance matching capacitances. Each first through hole is connected to a first signal interconnect at a position spaced part from the first signal electrode by a first interconnect length and each first via is connected to the second signal interconnect at a position spaced apart from the second signal electrode by a second interconnect length that is substantially equal with the first interconnect length.

Abstract: A semiconductor device includes a semiconductor chip, a plurality of external terminals, and a board. The board includes a first main surface in which a plurality of first electrodes electrically connected to the semiconductor chip are formed, a second main surface in which a plurality of second electrodes electrically connected to the plurality of external terminals are formed, and a plurality of interconnect layers, provided between the first main surface and the second main surface, for forming a plurality of signal paths that electrically connect the first electrode and the second electrode corresponding thereto. The interconnect layer includes a plurality of metal members which are dispersedly disposed at a distance shorter than an electromagnetic wavelength equivalent to a signal band of a signal supplied to the signal path, in the vicinity of a portion in which a structure of an interconnect for forming the signal path is changed.

Abstract: An interconnection structure includes a semiconductor chip, a mounting substrate on which the semiconductor chip is mounted, and a group of bonding wires provided to connect the semiconductor chip and the mounting substrate. The group of bonding wires includes: a first signal bonding wire contained in a first envelope and provided to propagate a signal; a first power supply bonding wire contained in the first envelope and applied with a first power supply voltage; and a second power supply bonding wire contained in a second envelope and applied with a second power supply voltage. One of the first envelope and the second envelope is arranged between the other of the first envelope and the second envelope and the mounting substrate.

Abstract: An impedance measurement method for circuits that has multiple power supply ports and a common ground shared by the multiple power supply ports, that includes finding multiple mutual impedances; finding approximate values for the ground impedance from the multiple mutual impedances; calculating multiple power supply port impedances from the approximate ground impedance values; and generating an equivalent circuit for the applicable circuit based on the ground impedances.

Abstract: When the impedance of a first circuit is deviated from a standard value, a second circuit is designed for generating a second reflected wave to cancel a first reflected wave generated by the first circuit. Individual structural parts in a transmission line are intentionally designed to be deviated from a standard impedance reversely under a fine control. By this method, the impedance matching between the input and output impedance of the semiconductor element and the transmission line is achieved. As a result, the terminal impedance of the component of the semiconductor circuit and the semiconductor package substrate is adjusted to 50 Ohm, so that a good signal property can be obtained.

Abstract: An interconnection structure includes a semiconductor chip, a mounting substrate on which the semiconductor chip is mounted, and a group of bonding wires provided to connect the semiconductor chip and the mounting substrate. The group of bonding wires includes: a first signal bonding wire contained in a first envelope and provided to propagate a signal; a first power supply bonding wire contained in the first envelope and applied with a first power supply voltage; and a second power supply bonding wire contained in a second envelope and applied with a second power supply voltage. One of the first envelope and the second envelope is arranged between the other of the first envelope and the second envelope and the mounting substrate.

Abstract: An interconnection structure includes: first and second differential signal interconnections provided to transmit a differential signal; and first and second voltage interconnections applied with predetermined voltages. The first voltage interconnection, the first differential signal interconnection, the second differential signal interconnection and the second voltage interconnection are arranged in this order. An interval between the first and second differential signal interconnections is longer than an interval between the first voltage interconnection and the first differential signal interconnection and is longer than an interval between the second differential signal interconnection and the second voltage interconnection.

Abstract: A package substrate includes: a plurality of electrodes configured to be electrically connected to a semiconductor chip; a plurality of wiring layers configured to be stacked; and a plurality of vias configured to electrically connect a plurality of planes formed in the plurality of wiring layers. A power supply via included in the plurality of vias electrically connects a power supply plane included in the plurality of planes to a power supply electrode included in the plurality of electrodes. The power supply plane is supplied with a power supply voltage. A passing wiring layer included in the plurality of wiring layers, through which the power supply via passes, includes: grid ground planes configured to surround the power supply via. The grid ground planes are electrically connected to a ground plane included in the plurality of planes through a ground via included in the plurality of vias. The ground plane is grounded.

Abstract: An impedance measurement method for circuits that has multiple power supply ports and a common ground shared by the multiple power supply ports, that includes finding multiple mutual impedances; finding approximate values for the ground impedance from the multiple mutual impedances; calculating multiple power supply port impedances from the approximate ground impedance values; and generating an equivalent circuit for the applicable circuit based on the ground impedances.

Abstract: When the impedance of a first circuit is deviated from a standard value, a second circuit is designed for generating a second reflected wave to cancel a first reflected wave generated by the first circuit. Individual structural parts in a transmission line are intentionally designed to be deviated from a standard impedance reversely under a fine control. By this method, the impedance matching between the input and output impedance of the semiconductor element and the transmission line is achieved. As a result, the terminal impedance of the component of the semiconductor circuit and the semiconductor package substrate is adjusted to 50 Ohm, so that a good signal property can be obtained.

Abstract: A plurality of film insulators having conductive patterns that are formed on surfaces and conductive vias that pass through the film insulators in the direction of thickness are stacked together and collectively subjected to pressure and heat to be formed as a single unit. On one outermost layer of the multilayer board that has been thus formed, a plurality of connection terminals are exposed to the outside, connection bumps of an LSI chip being secured to these connection terminals. On the outermost layer of the opposite side, a multiplicity of metal pads are provided, and a solder ball is secured on each metal pad to form a ball grid array (BGA) structure for connecting to a motherboard.

Abstract: An impedance measuring apparatus includes a plurality of RF (radio frequency) probes; a plurality of rotation mechanisms coupled to the plurality of RF probes, respectively; a processing unit, and a mechanical controller. The mechanical controller controls the plurality of rotation mechanisms and the plurality of RF probes to measure package RF signals between terminals formed on a package substrate. The processing unit measures calibration RF signals between terminals formed on at least one calibration substrate; determines RF impedances of the package substrate from the package RF signals and phase differences corresponding to a thickness of the package substrate and distances between the terminals on the package substrate from the calibration RF signals, and calibrates the RF impedances based on the phase differences.

Abstract: An impedance measuring apparatus includes a plurality of RF (radio frequency) probes; a plurality of rotation mechanisms coupled to the plurality of RF probes, respectively; a processing unit, and a mechanical controller. The mechanical controller controls the plurality of rotation mechanisms and the plurality of RF probes to measure package RF signals between terminals formed on a package substrate. The processing unit measures calibration RF signals between terminals formed on at least one calibration substrate; determines RF impedances of the package substrate from the package RF signals and phase differences corresponding to a thickness of the package substrate and distances between the terminals on the package substrate from the calibration RF signals, and calibrates the RF impedances based on the phase differences.

Abstract: A plurality of film insulators having conductive patterns that are formed on surfaces and conductive vias that pass through the film insulators in the direction of thickness are stacked together and collectively subjected to pressure and heat to be formed as a single unit. On one outermost layer of the multilayer board that has been thus formed, a plurality of connection terminals are exposed to the outside, connection bumps of an LSI chip being secured to these connection terminals. On the outermost layer of the opposite side, a multiplicity of metal pads are provided, and a solder ball is secured on each metal pad to form a ball grid array (BGA) structure for connecting to a motherboard.

Abstract: A semiconductor device is capable of reducing the parasitic resistance thereof without using any expensive special technique; increasing any leak current thereof; and, decreasing a gate breakdown strength thereof. In the device, for example, an undoped InGaAs layer serving as a channel layer is formed on a semi-insulating GaAs layer or the like. A first n-type AlGaAs layer, a second n-type AlGaAs layer and a third n-type AlGaAs layer are successively piled up on the undoped InGaAs layer in this order to form a carrier supply layer, wherein the second n-type AlGaAs layer is the lowest in impurity concentration among the first n-type AlGaAs layer, the second n-type AlGaAs layer, and the thirst n-type AlGaAs layer.

Abstract: There is provided a semiconductor memory device including a memory cell array having a plurality of multiple logical value memory cells arranged in a matrix, each memory cell storing a plurality of charge conditions each representing a logical value, a word line for selecting a memory cell in a column direction, a bit line for selecting a memory cell in a row direction, and a reading circuit for reading data stored in a selected memory, wherein the reading circuit includes a semiconductor superlattice including at least two sub-band levels under a continuation band, the semiconductor superlattice receiving bit line signals transmitted from the bit line, and transmitting an output signal each time when the bit line signal passes over each of the sub-band levels, and a counter for counting the output signals to output read logical values.

Abstract: A semiconductor device includes (a) a first conductivity type semiconductor substrate having a plurality of trenches formed therein, the trenches defining a plurality of device regions between adjacent trenches, (b) a second conductivity type diffusion layer formed at least around an outer surface of each of the device regions, (c) an insulating film formed on the inner surface of each of the trenches to cover a part of the second conductivity type diffusion layer therewith, (d) a plate electrode formed within each of the trenches, (e) a gate electrode formed above the second conductivity type diffusion layer and (f) a gate insulating film interposed between the gate electrode and the second conductivity type diffusion layer to isolate the gate electrode from the second conductivity type diffusion layer. This semiconductor device eliminates the need for the second conductivity type diffusion layer to serve as a capacitor electrode in contact with a switching transistor.

Abstract: In a DRAM memory cell comprising one capacitor having a capacitor electrode and an opposing electrode, and one insulated gate field effect transistor formed in a semiconductor substrate and having a pair of source/drain regions, one of which is connected to the capacitor electrode of the capacitor. A double gate thin film transistor having the same channel conductivity type as that of the insulated gate field effect transistor, is formed above the insulated gate field effect transistor. A first gate electrode of the thin film transistor is constituted of a gate electrode of the insulated gate field effect transistor, and a second gate electrode of the thin film transistor is constituted of the capacitor electrode of the capacitor. A source region of the thin film transistor and the other of the pair of source/drain regions of the insulated gate field effect transistor is connected to a bit line, and a drain region of the thin film transistor is connected to a power supply line.