Patents by Inventor Ryuji Hada
Ryuji Hada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8730250Abstract: An image processor includes a video input unit that counts the number of input pixel data and a command fetch/issue unit calculates, when a command including information concerning a relative position register in which a delay amount from input of pixel data until execution of a command is stored is fetched, a pixel position of processing target pixel data based on the delay amount and a count result and determines, based on the calculated pixel position, whether signal processing should be performed or specifies an operand used in arithmetic operation.Type: GrantFiled: August 13, 2009Date of Patent: May 20, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Yasuki Tanabe, Takashi Miyamori, Shunichi Ishiwata, Katsuyuki Kimura, Takahisa Wada, Keiri Nakanishi, Masato Sumiyoshi, Ryuji Hada
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Patent number: 8413123Abstract: According to an embodiment, a compiling device compiling a source program written so as to use a frame memory includes a processing delay amount calculator configured to calculate respective processing delay amounts between a plurality of process tasks in the source program on the basis of processing states of pieces of data processed by the process tasks. The compiling device also includes a line memory amount calculator configured to calculate respective line memory sizes required for each of the process tasks on the basis of an access range of a frame memory from which the process task reads data and an instruction code converter configured to convert the plurality of process tasks to instruction codes executable in a pipeline on the basis of the processing delay amounts and the line memory sizes.Type: GrantFiled: September 7, 2010Date of Patent: April 2, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Yasuki Tanabe, Takashi Miyamori, Shunichi Ishiwata, Katsuyuki Kimura, Keiri Nakanishi, Masato Sumiyoshi, Ryuji Hada
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Publication number: 20130069961Abstract: A projector of an embodiment is provided with: an input line memory which holds an input image signal corresponding to one line; an image processor which generates an intermediate image signal correction-processed according to distortion of a projection lens, using the input image signal transferred from the input line memory; an output line memory which holds the intermediate image signal corresponding to one line; and an LCOS which guides light radiated from a light source to the projection lens in accordance with the intermediate image signal. The image processor is provided with an input supplementation buffer which stores the input image signals of a plurality of lines, an input data buffer which stores input image signals required to generate the intermediate image signal corresponding to one line, and a number-of-supplementary-lines calculator which calculates the number of supplementary lines of the input image signals.Type: ApplicationFiled: March 15, 2012Publication date: March 21, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yutaka Ota, Ryuji Hada
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Patent number: 8345113Abstract: An image processing apparatus has: a data memory configured to store image data; an RP register configured to hold a two-dimensional address indicating a position of an RP in a frame of image data; and an RP control section configured to control the two-dimensional address held by the RP register on the basis of the width and height of the frame. Furthermore, the image processing apparatus has an address calculation unit configured to, when reading target pixel data is read from the data memory on the basis of an instruction code provided with a field for specifying a two-dimensional relative position from the RP by a combination of two immediate values, calculate an address at which the reading target pixel data is stored, on the basis of the two-dimensional address, the combination of immediate values and the width of the frame.Type: GrantFiled: July 30, 2009Date of Patent: January 1, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Keiri Nakanishi, Takashi Miyamori, Shunichi Ishiwata, Katsuyuki Kimura, Takahisa Wada, Masato Sumiyoshi, Yasuki Tanabe, Ryuji Hada
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Patent number: 8176290Abstract: A memory controller, on receiving a write request to write write-data into an address of a second memory region issued by a processor, determines whether read-data requested to be read from an address of a first memory region by the processor is matched with the write-data requested to be written into the address of the second memory region, and if the read-data is matched with the write-data, prevents the write-data from being written into the address of the second memory region.Type: GrantFiled: June 11, 2009Date of Patent: May 8, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Takahisa Wada, Katsuyuki Kimura, Shunichi Ishiwata, Takashi Miyamori, Ryuji Hada, Keiri Nakanishi, Yasuki Tanabe, Masato Sumiyoshi
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Publication number: 20110138371Abstract: According to an embodiment, a compiling device compiling a source program written so as to use a frame memory includes a processing delay amount calculator configured to calculate respective processing delay amounts between a plurality of process tasks in the source program on the basis of processing states of pieces of data processed by the process tasks. The compiling device also includes a line memory amount calculator configured to calculate respective line memory sizes required for each of the process tasks on the basis of an access range of a frame memory from which the process task reads data and an instruction code converter configured to convert the plurality of process tasks to instruction codes executable in a pipeline on the basis of the processing delay amounts and the line memory sizes.Type: ApplicationFiled: September 7, 2010Publication date: June 9, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Yasuki TANABE, Takashi Miyamori, Shunichi Ishiwata, Katsuyuki Kimura, Keiri Nakanishi, Masato Sumiyoshi, Ryuji Hada
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Publication number: 20100229162Abstract: A compiling apparatus includes an instruction-sequence-hierarchy-graph generating unit that generates an instruction sequence hierarchy graph by arraying unit graphs, to each of which a data path realized by a plurality of microinstructions included in one instruction sequence is to be allocated and in each of which function units included in a target processor are a node and a data line between the function units is an edge, to correspond to an execution order of a plurality of instruction sequences and by connecting arrayed unit graphs with an edge corresponding to a hardware path capable of establishing a data path across the instruction sequences; a data path allocating unit that allocates a data path to each of the unit graphs constituting the instruction sequence hierarchy graph; and an object program output unit that generates an instruction sequence group based on the data path allocated to the instruction sequence hierarchy graph.Type: ApplicationFiled: September 15, 2009Publication date: September 9, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Ryuji HADA, Takashi Miyamori, Keiri Nakanishi, Masato Sumiyoshi, Takahisa Wada, Yasuki Tanabe, Katsuyuki Kimura, Shunichi Ishiwata
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Publication number: 20100211758Abstract: A microprocessor that can perform sequential processing in data array unit includes: a load store unit that loads, when a fetched instruction is a load instruction for data, a data sequence including designated data from a data memory in memory width unit and specifies, based on an analysis result of the instruction, data scheduled to be designated in a load instruction in future; and a data temporary storage unit that stores use-scheduled data as the data specified by the load store unit.Type: ApplicationFiled: December 29, 2009Publication date: August 19, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masato Sumiyoshi, Takashi Miyamori, Shunichi Ishiwata, Katsuyuki Kimura, Takahisa Wada, Keiri Nakanishi, Yasuki Tanabe, Ryuji Hada
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Publication number: 20100110289Abstract: An image processor includes a video input unit that counts the number of input pixel data and a command fetch/issue unit calculates, when a command including information concerning a relative position register in which a delay amount from input of pixel data until execution of a command is stored is fetched, a pixel position of processing target pixel data based on the delay amount and a count result and determines, based on the calculated pixel position, whether signal processing should be performed or specifies an operand used in arithmetic operation.Type: ApplicationFiled: August 13, 2009Publication date: May 6, 2010Applicant: Kabushiki Kaisha ToshibaInventors: Yasuki Tanabe, Takashi Miyamori, Shunichi Ishiwata, Katsuyuki Kimura, Takahisa Wada, Keiri Nakanishi, Masato Sumiyoshi, Ryuji Hada
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Publication number: 20100110213Abstract: An input unit that sequentially writes a digital image signal to be input in a first buffer while counting number of pixels of the digital image signal, and that writes the written digital image signal in a second buffer; and a command fetching/issuing unit that calculates a position of a pixel based on process delay information that is added to an image processing command and that indicates a delay amount required until image processing by the command is started since the input of the digital image signal, and a counter value indicating the number of pixels, and that issues the image processing command when the position of the pixel is in a valid area are included. Image processing is performed on pixels written in the second buffer based on the issued image processing command.Type: ApplicationFiled: September 2, 2009Publication date: May 6, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Katsuyuki KIMURA, Takashi MIYAMORI, Shunichi ISHIWATA, Takahisa WADA, Keiri NAKANISHI, Masato SUMIYOSHI, Yasuki TANABE, Ryuji HADA
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Publication number: 20100103282Abstract: An image processing apparatus has: a data memory configured to store image data; an RP register configured to hold a two-dimensional address indicating a position of an RP in a frame of image data; and an RP control section configured to control the two-dimensional address held by the RP register on the basis of the width and height of the frame. Furthermore, the image processing apparatus has an address calculation unit configured to, when reading target pixel data is read from the data memory on the basis of an instruction code provided with a field for specifying a two-dimensional relative position from the RP by a combination of two immediate values, calculate an address at which the reading target pixel data is stored, on the basis of the two-dimensional address, the combination of immediate values and the width of the frame.Type: ApplicationFiled: July 30, 2009Publication date: April 29, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Keiri NAKANISHI, Takashi Miyamori, Shunichi Ishiwata, Katsuyuki Kimura, Takahisa Wada, Masato Sumiyoshi, Yasuki Tanabe, Ryuji Hada
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Publication number: 20100030978Abstract: A memory controller controls a memory access to each memory region out of one or more memory regions in SIMD unit. The memory controller includes: a pointer-calculation hardware unit that increments by unit SIMD a value of an access control pointer corresponding to each of the memory regions at different timings corresponding to an access mode set beforehand in each memory region; and a memory-access-control hardware unit that calculates an access destination address in each of the memory regions based on a value of an access control pointer in the memory region, and causes a memory access in SIMD unit to be performed to the calculated access destination address.Type: ApplicationFiled: July 29, 2009Publication date: February 4, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Ryuji HADA, Takashi Miyamori, Shunichi Ishiwata, Katsuyuki Kimura, Takahisa Wada, Keiri Nakanishi, Masato Sumiyoshi, Yasuki Tanabe
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Publication number: 20100005271Abstract: A memory controller, on receiving a write request to write write-data into an address of a second memory region issued by a processor, determines whether read-data requested to be read from an address of a first memory region by the processor is matched with the write-data requested to be written into the address of the second memory region, and if the read-data is matched with the write-data, prevents the write-data from being written into the address of the second memory region.Type: ApplicationFiled: June 11, 2009Publication date: January 7, 2010Applicant: Kabushiki Kaisha ToshibaInventors: Takahisa WADA, Katsuyuki Kimura, Shunichi Ishiwata, Takashi Miyamori, Ryuji Hada, Keiri Nakanishi, Yasuki Tanabe, Masato Sumiyoshi