Patents by Inventor Ryuji Kohno

Ryuji Kohno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5959571
    Abstract: A radar device transmits an electric wave whose band is spread by a PN code, receives a reflected wave of the electric wave from an object 10, detects correlation between a received signal and a PN code which is delayed, and thereby detects the object. A receiving part 18 connects three receiving antennas 16a.about.16c sequentially one by one, thereby to receive a reflected wave from an object. The three receiving antennas are arranged having their directions so staggered that their antenna beam patterns partly overlap with each other. A correlation detection circuit 19 detects such a slide width that a value of correlation between a received signal received by each of the antennas and the PN code exceeds a predetermined threshold. An operation part 12 obtains an azimuth of an object based on the detected slide width and beam pattern characteristics of the antennas.
    Type: Grant
    Filed: December 11, 1997
    Date of Patent: September 28, 1999
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Yasushi Aoyagi, Toshihide Fukuchi, Kiyoshi Inoue, Ryuji Kohno
  • Patent number: 5724041
    Abstract: A radar device transmits by a transmitting part a wave whose band is spread by a PN code from a PN generator, receives at a receiving part a reflected wave from an object based on the wave and detects the object by detecting correlation between the received signal and the PN code. In this radar device, the received signal which is spread to a wide range is converted to a low-frequency band which is easy to be measured by a down converter so that a signal is generated when correlation is made by a delay of the PN code from a delay circuit, and generates a pulse signal through waveform shaping of the signal to detect the object and to measure its relative speed and distance at a processing part according to the pulse signal and the delay time.
    Type: Grant
    Filed: November 22, 1995
    Date of Patent: March 3, 1998
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Kiyoshi Inoue, Haruhiko Ishizu, Ryuji Kohno
  • Patent number: 5635756
    Abstract: A semiconductor device of a structure in which lateral surfaces of a semiconductor element and an element supporting member are bonded to each other without resorting to use of a base member on which the semiconductor element is disposed. Since thicknesses of the base member and a bonding resin provides no contribution to overall thickness of the semiconductor device, reduction of thickness thereof by 30 to 40% is made possible. In dependent on configuration of the element supporting member, the semiconductor device can be applied to large size elements, lead-on-chip structure (LOC) and others.
    Type: Grant
    Filed: January 6, 1995
    Date of Patent: June 3, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Ryuji Kohno, Makoto Kitano, Asao Nishimura
  • Patent number: 5608265
    Abstract: A semiconductor device, provided in a plastic encapsulated package, having a semiconductor chip, a lead and a member for electrically connecting them together. The semiconductor device has one or more first holes respectively extending from one surface of the package to a first side of the lead which is provided inside of the package, and has one or more second holes formed which are aligned with the first holes, respectively, in a manner such that each second hole is extended from the opposing surface of the package to a corresponding location on a second side of the lead and is aligned with a corresponding, opposing first hole, in the package, extending to the first side of the lead. These holes are provided as a plurality of sets of individual pairs of aligned holes respectively extending inwardly, from opposing surfaces of the package, to opposite sides of the corresponding leads.
    Type: Grant
    Filed: March 9, 1994
    Date of Patent: March 4, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Kitano, Asao Nishimura, Akihiro Yaguchi, Nae Yoneda, Ryuji Kohno, Naotaka Tanaka, Tetsuo Kumazawa
  • Patent number: 5569960
    Abstract: An electronic component unit is provided with two electronic components which are disposed in parallel with each other and each of which has an internal electric circuit therein. Electrode pads are provided on the opposed surfaces of the two electronic components and are electrically connected to the internal electric circuits. The pads on one of the electronic components are respectively electrically and mechanically connected to the corresponding pads on the other electronic component by solder bumps. The areas of the pads increase or decrease stepwise in the direction from the central portions toward the outer peripheral edges of the two electronic components, while the volumes of the solder bumps are constant. Alternatively, the volumes of the solder bumps decrease or increase in the direction from the central portions toward the outer peripheral edges of the two electronic components, while the areas of all pads are constant.
    Type: Grant
    Filed: May 10, 1995
    Date of Patent: October 29, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Tetsuo Kumazawa, Makoto Kitano, Akihiro Yaguchi, Ryuji Kohno, Naotaka Tanaka, Nae Yoneda, Ichiro Anjoh
  • Patent number: 5539250
    Abstract: A plastic-molded-type semiconductor device is provided wherein two semiconductor chips, having main surfaces on which electrodes and circuits are formed, are arranged to face each other. A lead frame is placed between these two semiconductor chips and electrically connected to their electrodes, and a plastic package is formed by plastic-sealing the above components. To provide for secure and convenient electrical connections between the electrodes on the semiconductor chips and the lead frame, wiring patterns are provided on the main surfaces of the semiconductor chips through the intermediation of insulating films. With this structure, it is possible for two large-sized semiconductor chips having electrodes in their middle sections to be encased in a single, relatively thin package.
    Type: Grant
    Filed: June 11, 1991
    Date of Patent: July 23, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Kitano, Asao Nishimura, Akihiro Yaguchi, Ryuji Kohno, Nae Yoneda
  • Patent number: 5391916
    Abstract: A semiconductor device of a structure in which lateral surfaces of a semiconductor element and an element supporting member are bonded to each other without resorting to use of a base member on which the semiconductor element is disposed. Since thicknesses of the base member and a bonding resin provides no contribution to overall thickness of the semiconductor device, reduction of thickness thereof by 30 to 40% is made possible. In dependence on configuration of the element supporting member, the semiconductor device can be applied to large size elements, lead-on-chip structure (LOC) and others.
    Type: Grant
    Filed: June 14, 1993
    Date of Patent: February 21, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Ryuji Kohno, Makoto Kitano, Asao Nishimura
  • Patent number: 5357139
    Abstract: In a package for DRAM, plastic is included between the common signal inner leads (bus bar inner leads) and insulating films arranged in the central part of a semiconductor chip. Thus, the deformation of plastic at the upper edge of the common signal inner leads is reduced and no great stress is generated at this portion. Accordingly, plastic cracking can be prevented.
    Type: Grant
    Filed: September 8, 1993
    Date of Patent: October 18, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Akihiro Yaguchi, Asao Nishimura, Makoto Kitano, Ryuji Kohno, Nae Yoneda, Ichiro Anjoh, Gen Murakami
  • Patent number: 5347429
    Abstract: A plastic-molded-type semiconductor device includes a plurality of semiconductor chips, metallic wires connected to the semiconductor chips, leads connected to the metallic wires, and an insulating member interposed between the semiconductor chips and sealed in a resin member. Circuit formed surfaces of the semiconductor chips are directed in the same direction, and one or more of the semiconductor chips serve as a base on which the other semiconductor chips are mounted through the insulating member. One ends of the leads are bonded to the insulating member, and electrodes pad of each semiconductor chip are not covered by the other semiconductor chips, the insulating member and the leads, and therefore are exposed to the surface of the insulating member. In this device, the provision of a tab is omitted, and the laminated chips can be contained in a package thinner than a conventional package.
    Type: Grant
    Filed: May 28, 1993
    Date of Patent: September 13, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Ryuji Kohno, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Nae Yoneda
  • Patent number: 5296737
    Abstract: A semiconductor device comprises a plurality of semiconductor chips; electrodes formed on circuit surfaces of said plurality of semiconductor chips; inner leads made of a metal foil and bonded at first ends thereof to the electrodes, outer leads each having a predetermined surface at a first end thereof bonded to a second end of at least one of the inner leads, and a sealing material sealing said plurality of semiconductor chips, the electrodes, the inner leads, and part of each of the outer leads. The semiconductor chips are laminated in such a manner that those surfaces of the semiconductor chips on which their respective circuits are formed are disposed in facing relation to each other. This provides a semiconductor device which is excellent in assembling efficiency.
    Type: Grant
    Filed: September 6, 1991
    Date of Patent: March 22, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Nae Yoneda, Ryuji Kohno, Gen Murakami, Ichiro Anjoh
  • Patent number: 5295045
    Abstract: A plastic-molded-type semiconductor device having a high degree of integration encases a plurality of semiconductor chips in a package unit with each chip situated perpendicular to the substrate for mounting. On a surface of each chip containing circuits or on a reverse surface of the same, a lead frame is attached with an insulating material interposed therebetween. The chip and lead frame are connected with each other by using wire. The lead frame is arranged perpendicularly to another lead frame provided in parallel and connected therewith by welding. A printed circuit board may be used in place of said latter lead frame. By arranging the chips in projections made of resin, the thermal resistance of the semiconductor device is decreased. The present invention is particularly effective for a memory IC.
    Type: Grant
    Filed: November 14, 1991
    Date of Patent: March 15, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Kitano, Asao Nishimura, Akihiro Yaguchi, Nae Yoneda, Maya Obata, Ryuji Kohno, Mitsuaki Haneda
  • Patent number: 5293068
    Abstract: An encapsulated semiconductor device has a chip, a chip pad having through holes and also conducting patterns corresponding to an electrode pad of the chip, and leads. An arbitrary external terminal arrangement is obtained by combining a wire bonding operation between the conducting pattern and lead. Wire bonding is advantageously performed between the leads and electrode pads of the semiconductor chip arranged at arbitrary positions. The degree of freedom in designing areas of the chips and also a printed circuit board is improved so that a high packaging density is achieved and furthermore the printed circuit board is made compact.
    Type: Grant
    Filed: October 13, 1992
    Date of Patent: March 8, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Ryuji Kohno, Makoto Kitano, Asao Nishimura, Akihiro Yaguchi, Sueo Kawai
  • Patent number: 5256903
    Abstract: A plastic encapsulated semiconductor device containing one or more of insulating films. Uneven surfaces, such as recesses and roughened surfaces, are strategically provided on peripheral side (edge) surfaces of the insulating films. As a result, therefore, an interface separation does not easily occur between the side surfaces of the insulating films and the encapsulating resin. If such an interface separation should occur, it cannot develop easily. Thus, it is possible to obtain a plastic encapsulated semiconductor device of a high level of reliability even when the largest possible semiconductor element is mounted therein within limited outside dimensions.
    Type: Grant
    Filed: November 26, 1991
    Date of Patent: October 26, 1993
    Assignee: Hitachi Ltd.
    Inventors: Maya Obata, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Ryuji Kohno, Nae Yoneda, Ichiro Anjoh, Gen Murakami
  • Patent number: 5194935
    Abstract: The plastic encapsulated semiconductor device according to the present invention has a semiconductor chip, leads, and members for electrically connecting these parts to each other. A part of leads, the semiconductor chip and the connecting members are encapsulated with a plastic to form a package. The plate type plastic fins formed on the surface of and integrally with the package are divided in two directions perpendicular to each other thereby forming, for example, rows and columns of fins or fin segments, on the package surface. Therefore, the semiconductor device according to the present invention can be molded easily by a transfer molding. It has a high reliability with respect to the prevention of cracks in the plastic, and a low thermal resistance, and is most suitably used to obtain a high-density package mounting structure.
    Type: Grant
    Filed: January 29, 1991
    Date of Patent: March 16, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Kitano, Asao Nishimura, Akihiro Yaguchi, Nae Yoneda, Ryuji Kohno, Sueo Kawai, Gen Murakami, Ichio Shimizu
  • Patent number: 5159434
    Abstract: An encapsulated semiconductor device has a chip, a chip pad having through holes and also conducting patterns corresponding to an electrode pad of the chip, and leads. An arbitrary external terminal arrangement is obtained by combining a wire bonding operation between the conduting pattern and lead. Wire bonding is advantageously performed between the leads and electrode pads of the semiconductor chip arranged at arbitrary positions. The degree of freedom in designing areas of the chips and also a printed circuit board is improved so that a high packaging density is achieved and furthermore the printed circuit board is made compact.
    Type: Grant
    Filed: February 1, 1991
    Date of Patent: October 27, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Ryuji Kohno, Makoto Kitano, Asao Nishimura, Akihiro Yaguchi, Sueo Kawai
  • Patent number: 5093839
    Abstract: A frequency diversity receiving system is based on cancellation of a C/A (Clear/Acquisition) code in a GPS (Global Positioning System). Spread spectrum signals of a P code (Precision) code is picked up by removing, in an interference removal circuit, spread spectrum signals of the C/A code out of spread spectrum signals of L.sub.1 band which are transmitted from GPS satellites. A difference in relative delay times between the spread spectrum signals of the P code in L.sub.1 band and spread spectrum signals of the P code in L.sub.2 band, which are also transmitted from GPS satellites, is obtained in a modified DLL (Delay Locked Loop).
    Type: Grant
    Filed: January 2, 1991
    Date of Patent: March 3, 1992
    Assignee: Sokkisha Co., Ltd.
    Inventors: Ryuji Kohno, Hefeng Wang, Hideki Imai