Patents by Inventor Ryuji Kohno

Ryuji Kohno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6774654
    Abstract: A semiconductor inspecting apparatus having a plurality of electrical connection boards arranged in the inspecting apparatus and a plurality of probes respectively provided on a plurality of beams formed on a first board of said plurality of electrical connection boards, the probes being adapted to be individually brought into contact with a plurality of electrode pads of a semiconductor device for inspection, so as to inspect the semiconductor device while establishing electrical connection therebetween. A one-end supported beam is used as each of the beams, and each of the probes is formed at a portion shifted in a rectangular direction to a center line of a longitudinal direction of the one-end supported beam.
    Type: Grant
    Filed: December 12, 2002
    Date of Patent: August 10, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Masatoshi Kanamaru, Yoshishige Endo, Takanorr Aono, Ryuji Kohno, Toshio Miyatake, Hideyuki Aoki, Naoto Ban
  • Publication number: 20040145382
    Abstract: A probe structure is provided in which secondary electrodes of a main base material and probes are formed can be electrically connected to electrodes in a substrate side even when a lot of probes are formed in a large area, so that a lot of LSIs within a wafer can be tested in one lot in a wafer test process, and an efficiency of the test process can be improved. In the probe structure, an interposer constituted by a high rigid material is arranged between the main base material having the probes formed therein and the substrate side, and the secondary electrodes of the main base material having the probes formed therein are electrically connected to the electrodes in the substrate side via the interposer.
    Type: Application
    Filed: July 24, 2003
    Publication date: July 29, 2004
    Inventors: Ryuji Kohno, Tatsuya Nagata, Hiroya Shimizu, Toshio Miyatake, Hideo Miura
  • Patent number: 6768337
    Abstract: A plurality of circuit cells, a plurality of matrix switch sections and a plurality of switch sections for connecting between the plurality of circuit cells, all of which form a part of a circuit cell array, and a plurality of input/output cell sections arranged around the circuit cell array all change their circuit configurations in accordance with a configuration data to be supplied. In some of these circuit blocks, at least a part of the circuit thereof is fixed at a predetermined circuit configuration, and a conversion of the configuration data based on proprietary information regarding the fixed circuit is performed at a supplier of the configuration data. Thus, a differential configuration data for portions of the circuit other than the fixed circuit portion is generated and supplied to the integrated circuit.
    Type: Grant
    Filed: August 19, 2002
    Date of Patent: July 27, 2004
    Assignee: Sony Corporation
    Inventors: Ryuji Kohno, Kenichiro Akai, Yukitoshi Sanada, Robert Morelos-Zaragoza, Lachlan Michael
  • Publication number: 20040135593
    Abstract: A testing apparatus and a fabricating method of a semiconductor integrated circuit device for reducing the fabrication cost by placing, in the wafer level burn-in, divided contactors in equally contact with the full surface of wafer, enabling repair of each contactor and improving the yield of contactors. The cassette structure of the mechanical pressurizing system in the testing apparatus is structured with a plurality of divided silicon contactor blocks and a guide frame for integrating these blocks and employs the wafer full surface simultaneous contact system of the divided contactor integration type. Each probe of the silicon contactor is equally placed in contact in the predetermined pressure with each test pad of each chip of the test wafer by mechanically pressuring each silicon contactor block which moves individually, the test control signal is supplied to each chip and this test result signal is obtained for the wafer level burn-in test.
    Type: Application
    Filed: January 7, 2004
    Publication date: July 15, 2004
    Inventors: Naoto Ban, Masaaki Namba, Akio Hasebe, Yuji Wada, Ryuji Kohno, Akira Seito, Yasuhiro Motoyama
  • Patent number: 6763062
    Abstract: When the average received signal level falls below a given threshold level, a received level detecting/monitoring section informs a microprocessor of it. The microprocessor then collects information of the arrival direction and received power of desired radiation from each terminal station and the arrival direction and received power of undesired radiation from each source of undesired radiation and recalculates amplitude and phase weight values. The microprocessor rewrites weight values already entered into a weight value table by the recalculated weight values to thereby alter amplitude and phase weight values for antenna elements of an array antenna. Thereby, the directivity of the array antenna is subjected to optimum control according to variations in electromagnetic radiation propagation environment, allowing good radio communications at all times.
    Type: Grant
    Filed: May 23, 2000
    Date of Patent: July 13, 2004
    Assignees: Toshiba Tec Kabushiki Kaisha
    Inventors: Ryuji Kohno, Hiroki Mochizuki
  • Patent number: 6728294
    Abstract: A microprocessor reads the information such as directions of arrival about a desired wave and an undesired wave for every terminal station and for every hopping frequency, and their receiving powers, and the like, from a desired wave/undesired wave information inputting unit. On the basis of the information items, the microprocessor calculates the weight values of a transmitting section and a receiving section for every terminal station and every hopping frequency, and stores them in a weight value table. At the time of performing radio communication, the microprocessor reads the weight values of the receiving section and the transmitting section corresponding to every terminal station and every hopping frequency from the weight value table every time the frequency is hopped, and sets them in attenuators, and phase shifters. As a result, the optimum directivity pattern is formed for every hopping frequency, and high-quality communication can be thereby achieved.
    Type: Grant
    Filed: May 23, 2000
    Date of Patent: April 27, 2004
    Assignees: Toshiba Tec Kabushiki Kaisha
    Inventors: Ryuji Kohno, Hiroki Mochizuki
  • Patent number: 6714030
    Abstract: A semiconductor inspection apparatus which is possible to inspect a plurality of semiconductor devices collectively at one time, which has conventionally been difficult because of precision or the like of probes.
    Type: Grant
    Filed: March 18, 2003
    Date of Patent: March 30, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Ryuji Kohno, Hideo Miura, Yoshishige Endo, Masatoshi Kanamaru, Atsushi Hosogane, Hideyuki Aoki, Naoto Ban
  • Patent number: 6696849
    Abstract: A testing apparatus and a fabricating method of a semiconductor integrated circuit device for reducing the fabrication cost by placing, in the wafer level burn-in, divided contactors in equally contact with the full surface of wafer, enabling repair of each contactor and improving the yield of contactors. The cassette structure of the mechanical pressurizing system in the testing apparatus is structured with a plurality of divided silicon contactor blocks and a guide frame for integrating these blocks and employs the wafer full surface simultaneous contact system of the divided contactor integration type. Each probe of the silicon contactor is equally placed in contact in the predetermined pressure with each test pad of each chip of the test wafer by mechanically pressuring each silicon contactor block which moves individually, the test control signal is supplied to each chip and this test result signal is obtained for the wafer level burn-in test.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: February 24, 2004
    Assignee: Renesas Technology Corporation
    Inventors: Naoto Ban, Masaaki Namba, Akio Hasebe, Yuji Wada, Ryuji Kohno, Akira Seito, Yasuhiro Motoyama
  • Publication number: 20030227408
    Abstract: To realize an antenna apparatus capable of measuring a calibration factor accurately and further, capable of estimating an arrival direction of a received signal by composing a calibration circuit by using a directional coupler. The antenna system includes L-number of branch units, a calibration circuit and an operating unit. Each directional coupler composing the calibration circuit is structured symmetrically. Measuring the received signals Yti, i−1 and Yti, i+1 of i−1th and i+1th receivers, respectively, when an ith transmitter transmits a signal, on the basis of the first branch unit, the operating unit calculates a calibration factor at the ith branch unit as Hi=T1Ri/(TiR1)=Yt12Yt23−Yti−1,i/Yt21Yt32−Yti,i−1.
    Type: Application
    Filed: January 23, 2003
    Publication date: December 11, 2003
    Applicant: Sony Corporation
    Inventors: Yukitoshi Sanada, Ryuji Kohno
  • Patent number: 6660541
    Abstract: A method of manufacturing a semiconductor device includes forming process of forming a semiconductor element on a semiconductor wafer and testing process of testing electrical performance of the formed semiconductor element. The testing process includes process of electrically connecting a testing apparatus to an electrode pad formed on the semiconductor element to be tested. The testing apparatus has a probe-formed substrate including a plurality of beams having probes to be electrically connected to the electrode pads. The probe-formed substrate has a first beam having at least one probe for electrically connection with the electrode pad and a second beam having a number of probes for electrical connection with the electrode pads of which number is more than the number of the electrode pads electrically connected by said first beam.
    Type: Grant
    Filed: October 23, 2002
    Date of Patent: December 9, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Masatoshi Kanamaru, Yoshishige Endo, Takanori Aono, Ryuji Kohno, Hideyuki Aoki
  • Publication number: 20030215089
    Abstract: This invention provides a method and an apparatus for executing improved Boolean matrices based encryption and decryption. In a data communication system, a server generates a series of encrypted data message blocks C1, C2, . . , Cm from plain data blocks P1, P2, . . . , Pm, by computing Ci=K(Pi+K*iVT)Ki. A client receives the encrypted data and generates a series of plain data message blocks P1, P2, . . . , Pn; by computing Pi=K−1CiK*i+K*iVT.
    Type: Application
    Filed: April 10, 2003
    Publication date: November 20, 2003
    Inventors: Miodrag Mihaljevic, Ryuji Kohno
  • Publication number: 20030210781
    Abstract: This invention provides a method for executing an improved Boolean matrices based encryption, and a data communication system. In a data communication system, a server generates a series of encrypted data message blocks C1, C2, . . . , Cn from plain data blocks P1, P2, . . . , Pn, by computing Ci=K(Pi+KVKi)Kn+i+KVKi. A client receives the encrypted data and generates a series of plain data message blocks P1, P2, . . . , Pn; by computing Pi=K−1(Ci+KVKi)K−(n+i)+KVKi.
    Type: Application
    Filed: January 29, 2003
    Publication date: November 13, 2003
    Applicant: Sony Corporation
    Inventors: Miodrag Mihaljevic, Ryuji Kohno
  • Publication number: 20030203521
    Abstract: Dispersion of load may be kept within an allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane to a wafer by applying a pressure load to a plurality of places of a plane of pressure members on the side opposite from the wafer in a probe test step/burn-in test step which is one of semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit in the same time.
    Type: Application
    Filed: April 11, 2003
    Publication date: October 30, 2003
    Inventors: Ryuji Kohno, Tetsuo Kumazawa, Makoto Kitano, Akihiko Ariga, Yuji Wada, Naoto Ban, Shuji Shibuya, Yasuhiro Motoyama, Kunio Matsumoto, Susumu Kasukabe, Terutaka Mori, Hidetaka Shigi, Takayoshi Watanabe
  • Publication number: 20030189439
    Abstract: A semiconductor inspection apparatus which is possible to inspect a plurality of semiconductor devices collectively at one time, which has conventionally been difficult because of precision or the like of probes.
    Type: Application
    Filed: March 18, 2003
    Publication date: October 9, 2003
    Inventors: Ryuji Kohno, Hideo Miura, Yoshishige Endo, Masatoshi Kanamaru, Atsushi Hosogane, Hideyuki Aoki, Naoto Ban
  • Publication number: 20030179136
    Abstract: An array antenna comprising a plurality of antenna elements, multipliers for multiplying coefficients with transmission or reception signal and a calculator for calculating the coefficients for each multiplier. The calculator generates the coefficients in a proposed method such that the beampattern of the array antenna has a flat top mainlobe with an adjustable beamwidth and a predetermined sidelobe ratio.
    Type: Application
    Filed: December 2, 2002
    Publication date: September 25, 2003
    Inventors: Ryuji Kohno, Abreu Giuseppe
  • Patent number: 6614246
    Abstract: The invention provides a probe structure in which secondary electrodes of a main base material in which probes are formed can be electrically connected to electrodes in a substrate side even when a lot of probes are formed in a large area, so that a lot of LSIs within a wafer can be tested in one lot in a wafer test process, whereby an efficiency of the test process can be improved. In the probe structure, an interposer constituted by a high rigid material is arranged between the main base material having the probes formed therein and the substrate side, and the secondary electrodes of the main base material having the probes formed therein are electrically connected to the electrodes in the substrate side via the interposer.
    Type: Grant
    Filed: August 28, 2000
    Date of Patent: September 2, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Ryuji Kohno, Tatsuya Nagata, Hiroya Shimizu, Toshio Miyatake, Hideo Miura
  • Patent number: 6611859
    Abstract: A network comprises an IEEE 1394 sub-network serving as a wire-communication system at the high-level layer, and a plurality of radio-communication terminals (radio-communication nodes) which form DHCP clients. The IEEE 1394 sub-network constitutes an in-home LAN (Local Network Area). The IEEE 1394 sub-network includes antenna base stations each serving as a DHCP server. The antenna base stations have a pool comprising a predetermined number of addresses which are assigned automatically to radio-communication terminals (or DHCP clients) in a cell under control by each of the antenna base stations. In this case, the addresses in the pool controlled by the antenna base stations (DHCP servers) are varied among the servers according to a dynamic mobility distribution of radio-communication terminals. In this way, addresses can be utilized efficiently and, at the same time, it is possible to avoid a bus reset caused by a movement of a radio-communication terminal.
    Type: Grant
    Filed: February 25, 2000
    Date of Patent: August 26, 2003
    Assignee: Sony Corporation
    Inventor: Ryuji Kohno
  • Publication number: 20030142756
    Abstract: To provide a transmission apparatus and a communication system that transmit a plurality of transmission signals riding on different interfering transmission beams, separate and receive the transmission signal at the receiving side, and estimate the original transmission signal by maximum likelihood estimation based on the correlation among the received signals. A transmission apparatus which encodes the transmission signal by an encoding means to generate at least two transmission signals S1 and S2, modulates the signals to the carrier frequencies, weights them and supplies them to the antenna elements, and controls the weights to transmit the modulated output signals by beams partially overlapping each other in space.
    Type: Application
    Filed: April 9, 2002
    Publication date: July 31, 2003
    Inventors: Ryuji Kohno, Kazunori Watanabe, Kouji Ishii
  • Publication number: 20030128772
    Abstract: A wireless impulse transmitter that is for transmitting pulse trains to a plurality of receivers, includes a pulse selector, a pulse supplier, and a transmission unit. The pulse selector is for selecting, from a plurality of orthogonal pulse shapes assigned in a two-to-one correspondence with the receivers, pulse shapes corresponding to symbols of an input data stream. Each of the two pulse shapes assigned to each receiver represents either one or zero to the corresponding receiver. The pulse supplier is for supplying pulses in pulse shapes selected by the pulse selector. The transmission unit is for transmitting the pulses supplied from the pulse supplier in pulse trains, wherein pulses with pulse shapes assigned to different receivers are transmitted simultaneously.
    Type: Application
    Filed: July 22, 2002
    Publication date: July 10, 2003
    Inventors: Lachlan Michael, Mohammad Ghavami, Ryuji Kohno
  • Publication number: 20030122550
    Abstract: A semiconductor device testing apparatus is realized, which allows contactors to be positioned throughout the wafer surface highly accurately for uniform contact, testing a large-sized wafer, and cost reduction. A plurality of divided contactor blocks is formed with a positioning groove. The groove is used to position the plurality of contactor blocks with a positioning frame. Because the contactor blocks are divided into plurals, it is less likely that a partial surface distortion affects other portions to impair surface flatness as compared with the case where a plurality of non-divided contactors is formed integrally, and the plurality of contactor blocks can be brought into contact with a wafer to be tested uniformly. Additionally, even though abnormality is generated in a part of the contactor blocks, only the part of the contactor blocks is replaced. Therefore, replacement costs can be reduced as compared with the case where a plurality of non-divided contactors is formed integrally.
    Type: Application
    Filed: July 30, 2002
    Publication date: July 3, 2003
    Inventors: Masatoshi Kanamaru, Yoshishige Endo, Takanori Aono, Ryuji Kohno, Hiroya Shimizu, Naoto Ban, Hideyuki Aoki