Abstract: A semiconductor device includes non-volatile registers, each including a holding circuit to hold data in a volatile manner and a non-volatile element. An address is allocated to each of the non-volatile registers. A non-volatile register control circuit performs control such that, in response to a write instruction, data held in the holding circuit is written to the non-volatile element in the non-volatile register having the address specified by the instruction and in response to a load instruction, data held in the non-volatile element is held in the holding circuit in the non-volatile register having the address specified by the instruction.

Abstract: Provided is an operation method which can be applied to a PRAM, an ReRAM, and a solid electrolyte memory which stores error correction codes, each of which comprises of symbols, each of which comprises bits, and which codes allow error correction in units of symbols. In the operation method, the respective symbols are read by using different reference cells 12. When a correctable error is detected in read data from data cells forming the error correction codes and corresponding to an input address, a data in a data cell corresponding to the error bit is corrected for a first error symbol of an one bit error pattern, and data in a reference cell that is used to read the second error symbol are corrected for a second error symbol related to a multi-bit error pattern.

Abstract: A non-volatile logic circuit includes an input section, a control section and an output section. The input section has perpendicular magnetic anisotropy and has a ferromagnetic layer whose magnetization state is changeable. The control section includes a ferromagnetic layer. The output section is provided in a neighborhood of the input section and the control section and includes a magnetic tunnel junction element whose magnetization state is changeable. The magnetization state of the input section is changed based on the magnetization state. A magnetization state of the magnetic tunnel junction element of the output section which state is changed based on the magnetization state of the ferromagnetic material of the control section and the magnetization state of the ferromagnetic material of the input section.

Abstract: A semiconductor device comprises: reconfigurable logic circuit that includes plurality of resistance change elements; logical configuration of the reconfigurable logic circuit being decided depending on whether each of plurality of resistance change elements is in first resistance state or in second resistance state whose resistance value is lower than resistance value of first resistance state; resistance value monitor circuit that includes resistance change element pre-programmed to the first resistance state; the resistance value monitor circuit detecting whether or not pre-programmed resistance change element retains the first resistance state; and controller that, in case it is detected that resistance change element provided in resistance value monitor circuit doe not retain first resistance state, applies voltage used in programming from second resistance state to first resistance state to resistance change element retaining first resistance states, out of plurality of resistance change elements provid

Abstract: A magnetoresistive element 10 having a memory cell 100 according to the present invention contains a first lower terminal n1 and a second lower terminal n2 respectively connected to both ends of a conductive layer 3 whose longitudinal direction is different from the column direction (X direction). Further, the gates of the first transistors M1 respectively included in two memory cells among the plurality of memory cells 100 and adjacent to each other in a row direction (Y direction) are commonly connected to a first word line 14. As a result, without increase of the cell area, it becomes possible to reserve a margin in the dimension of the cell structure or in the process for MRMA.

Abstract: A logic gate has a magnetoresistive element, a magnetization state control unit and an output unit. The magnetoresistive element has a laminated structure having N (N is an integer not smaller than 3) magnetic layers and N?1 nonmagnetic layers that are alternately laminated. A resistance value of the magnetoresistive element varies depending on magnetization states of the N magnetic layers. The magnetization state control unit sets the respective magnetization states of the N magnetic layers depending on N input data. The output unit outputs output data that varies depending on the resistance value of the magnetoresistive element.

Abstract: A MRAM includes: first and second bit lines provided to extend in a first direction; a storage block including at least one magnetroresistive element for storing data; and a reading circuit. The reading circuit includes a first terminal electrically connected to the first bit line, and a second terminal electrically connected to the second bit line. The second terminal has a high impedance preventing a steady-state current from flowing into at a time of a reading operation. The reading circuit supplies a reading current from the first terminal to the first bit line at the time of the reading operation. The storage block is configured such that the reading current flows from the first bit line to the magnetroresistive element and the magnetroresistive element is connected to the second bit line at the time of the reading operation. The reading circuit controls the reading current on the basis of a voltage applied to the second terminal through the second bit line.

Abstract: A nonvolatile latch circuit includes: a latch circuit; a first magnetoresistance element and a second magnetoresistance element; and a current supply portion. The latch circuit temporarily holds data. Each of the first magnetoresistance element and the second magnetoresistance element includes a first magnetic layer and a second magnetic layer that are stacked with an insulating film sandwiched therebetween. The current supply portion complementarily changes magnetization states of the first magnetoresistance element and the second magnetoresistance element based on a state of the latch circuit. The first magnetic layer of the first magnetoresistance element and the first magnetic layer of the second magnetoresistance element are series-connected to each other in. The latch circuit has a function that brings data corresponding to the magnetization states to data held by the latch circuit.

Abstract: A nonvolatile latch circuit includes: first and second inverters cross-coupled to hold 1-bit data; first and second magnetoresistive elements each having first to third terminals; and a current supply circuitry configured to supply a magnetization reversal current for changing the magnetization states of the first and second maqnetoresistive elements in response to the 1-bit data. The power terminal of the first inverter is connected to the first terminal of the first magnetoresistive element and the power terminal of the second inverter is connected to the first terminal of the second magnetoresistive element. The current supply circuitry is configured to supply the magnetization reversal current to the second terminals of the first and second magnetoresistive elements. The third terminal of the first magnetoresistive element is electrically connected to the third terminal of the second magnetoresistive element.

Abstract: A non-volatile logic circuit includes an input section, a control section and an output section. The input section has perpendicular magnetic anisotropy and has a ferromagnetic layer whose magnetization state is changeable. The control section includes a ferromagnetic layer. The output section is provided in a neighborhood of the input section and the control section and includes a magnetic tunnel junction element whose magnetization state is changeable. The magnetization state of the input section is changed based on the magnetization state. A magnetization state of the magnetic tunnel junction element of the output section which state is changed based on the magnetization state of the ferromagnetic material of the control section and the magnetization state of the ferromagnetic material of the input section.

Abstract: An MRAM according to the present invention has: a memory cell array; a first word line and a second word line each connected to a group of memory cells arranged in a first direction; a plurality of blocks arranged in a matrix form; a common word line connected to a group of blocks arranged in the first direction; and a bit line pair connected to a group of blocks arranged in a second direction. Each block has a plurality of memory cells, and each memory cell has a first transistor and a magnetoresistance element. Each block further has a second transistor to which the plurality of memory cells are connected in parallel. A gate of the second transistor is connected to the common word line. A gate of the first transistor is connected to the first word line. One of source/drain of the first transistor is connected to the first bit line, and the other thereof is connected to one end of the magnetoresistance element and connected to the second bit line through the second transistor.

Abstract: A logic gate 40 according to the present invention has a magnetoresistive element 1, a magnetization state control unit 50 and an output unit 60. The magnetoresistive element 1 has a laminated structure having N (N is an integer not smaller than 3) magnetic layers 10 and N?1 nonmagnetic layers that are alternately laminated. A resistance value R of the magnetoresistive element 1 varies depending on magnetization states of the N magnetic layers 10. The magnetization state control unit 50 sets the respective magnetization states of the N magnetic layers 10 depending on N input data. The output unit 60 outputs an output data that varies depending on the resistance value R of the magnetoresistive element 1.

Abstract: A magnetoresistive element includes a free layer a pinned layer; a nonmagnetic layer interposed between the free layer and the pinned layer; and two magnetic layers arranged adjacent to the free layer on an opposite side to the pinned layer. The free layer includes: a first magnetic layer, a second magnetic layer, and a first nonmagnetic layer interposed between the first magnetic layer and the second magnetic layer. Magnetization of the first magnetic layer and magnetization of the second magnetic layer are antiferromagnetically coupled. One of the two magnetic layers is in contact with one end of the free layer in a long-axis direction, and the other of the two magnetic layers is in contact with the other end of the free layer in the long-axis direction.

Abstract: Provided is an operation method which can be applied to a PRAM, an ReRAM, and a solid electrolyte memory which stores error correction codes, each of which comprises of symbols, each of which comprises bits, and which codes allow error correction in units of symbols. In the operation method, the respective symbols are read by using different reference cells 12. When a correctable error is detected in read data from data cells forming the error correction codes and corresponding to an input address, a data in a data cell corresponding to the error bit is corrected for a first error symbol of an one bit error pattern, and data in a reference cell that is used to read the second error symbol are corrected for a second error symbol related to a multi-bit error pattern.

Abstract: A nonvolatile latch circuit includes: first and second inverters cross-coupled to hold 1-bit data; first and second magnetoresistive elements each having first to third terminals; and a current supply circuitry configured to supply a magnetization reversal current for changing the magnetization states of the first and second maqnetoresistive elements in response to the 1-bit data. The power terminal of the first inverter is connected to the first terminal of the first magnetoresistive element and the power terminal of the second inverter is connected to the first terminal of the second magnetoresistive element. The current supply circuitry is configured to supply the magnetization reversal current to the second terminals of the first and second magnetoresistive elements. The third terminal of the first magnetoresistive element is electrically connected to the third terminal of the second magnetoresistive element.

Abstract: A nonvolatile latch circuit includes: a latch circuit; a first magnetoresistance element and a second magnetoresistance element; and a current supply portion. The latch circuit temporarily holds data. Each of the first magnetoresistance element and the second magnetoresistance element includes a first magnetic layer and a second magnetic layer that are stacked with an insulating film sandwiched therebetween. The current supply portion complementarily changes magnetization states of the first magnetoresistance element and the second magnetoresistance element based on a state of the latch circuit. The first magnetic layer of the first magnetoresistance element and the first magnetic layer of the second magnetoresistance element are series-connected to each other in. The latch circuit has a function that brings data corresponding to the magnetization states to data held by the latch circuit.

Abstract: A MRAM includes: first and second bit lines provided to extend in a first direction; a storage block including at least one magnetroresistive element for storing data; and a reading circuit. The reading circuit includes a first terminal electrically connected to the first bit line, and a second terminal electrically connected to the second bit line. The second terminal has a high impedance preventing a steady-state current from flowing into at a time of a reading operation. The reading circuit supplies a reading current from the first terminal to the first bit line at the time of the reading operation. The storage block is configured such that the reading current flows from the first bit line to the magnetroresistive element and the magnetroresistive element is connected to the second bit line at the time of the reading operation. The reading circuit controls the reading current on the basis of a voltage applied to the second terminal through the second bit line.

Abstract: An MRAM according to the present invention has: a memory cell array; a first word line and a second word line each connected to a group of memory cells arranged in a first direction; a plurality of blocks arranged in a matrix form; a common word line connected to a group of blocks arranged in the first direction; and a bit line pair connected to a group of blocks arranged in a second direction. Each block has a plurality of memory cells, and each memory cell has a first transistor and a magnetoresistance element. Each block further has a second transistor to which the plurality of memory cells are connected in parallel. A gate of the second transistor is connected to the common word line. A gate of the first transistor is connected to the first word line. One of source/drain of the first transistor is connected to the first bit line, and the other thereof is connected to one end of the magnetoresistance element and connected to the second bit line through the second transistor.

Abstract: A magnetoresistive element includes a free layer a pinned layer; a nonmagnetic layer interposed between the free layer and the pinned layer; and two magnetic layers arranged adjacent to the free layer on an opposite side to the pinned layer. The free layer includes: a first magnetic layer, a second magnetic layer, and a first nonmagnetic layer interposed between the first magnetic layer and the second magnetic layer. Magnetization of the first magnetic layer and magnetization of the second magnetic layer are antiferromagnetically coupled. One of the two magnetic layers is in contact with one end of the free layer in a long-axis direction, and the other of the two magnetic layers is in contact with the other end of the free layer in the long-axis direction.