Abstract: There is provided an SOI-MISFET including: an SOI layer; a gate electrode provided on the SOI layer interposing a gate insulator; and a first elevated layer provided higher in height from the SOI layer than the gate electrode at both sidewall sides of the gate electrode on the SOI layer so as to constitute a source and drain. Further, there is also provided a bulk-MISFET including: a gate electrode provided on a silicon substrate interposing a gate insulator thicker than the gate insulator of the SOI MISFET; and a second elevated layer configuring a source and drain provided on a semiconductor substrate at both sidewalls of the gate electrode. The first elevated layer is thicker than the second elevated layer, and the whole of the gate electrodes, part of the source and drain of the SOI-MISFET, and part of the source and drain of the bulk-MISFET are silicided.

Abstract: Performance of a semiconductor device having a MIS transistor is improved. A semiconductor device includes: a pair of source/drain regions each formed by stacking a semiconductor layer on a main surface of a silicon substrate; a sidewall insulating film covering each sidewall of the source/drain regions; a gate electrode arranged so as to interpose a gate insulating film on the main surface of the silicon substrate at a position sandwiched by the sidewall insulating films in a plane; and extension regions formed to extend from a portion below and lateral to the gate electrode to a portion below and lateral to each of the source/drain regions, wherein a sidewall of the sidewall insulating film being adjacent to the gate insulating film and the gate electrode has an inclination of a forward tapered shape.

Abstract: Performance of a semiconductor device having a MIS transistor is improved. A semiconductor device includes: a pair of source/drain regions each formed by stacking a semiconductor layer on a main surface of a silicon substrate; a sidewall insulating film covering each sidewall of the source/drain regions; a gate electrode arranged so as to interpose a gate insulating film on the main surface of the silicon substrate at a position sandwiched by the sidewall insulating films in a plane; and extension regions formed to extend from a portion below and lateral to the gate electrode to a portion below and lateral to each of the source/drain regions, wherein a sidewall of the sidewall insulating film being adjacent to the gate insulating film and the gate electrode has an inclination of a forward tapered shape.

Abstract: In an SOI-MISFET that operates with low power consumption at a high speed, an element area is reduced. While a diffusion layer region of an N-conductivity type MISFET region of the SOI type MISFET and a diffusion layer region of a P-conductivity type MISFET region of the SOI type MISFET are formed as a common region, well diffusion layers that apply substrate potentials to the N-conductivity type MISFET region and the P-conductivity type MISFET region are separated from each other by an STI layer. The diffusion layer regions that are located in the N- and P-conductivity type MISFET regions) and serve as an output portion of a CMISFET are formed as a common region and directly connected by silicified metal so that the element area is reduced.

Abstract: It is an object of the present invention to provide a method of manufacturing an SOI wafer at low cost and with high yield. It is another object of the present invention to provide a semiconductor device including also bulk type MISFETs used as high voltage regions and a method of manufacturing the same without using complicated processes and increasing the size of a semiconductor chip. The method of manufacturing a semiconductor device comprises selectively epitaxially growing a single-crystal Si layer and continuously performing the epitaxial growth without bringing a substrate temperature increased during the growth to room temperature even once. An epitaxially grown surface is then etched and planarized. The substrate temperature is then cooled down to the room temperature.

Abstract: There is provided an SOI-MISFET including: an SOI layer; a gate electrode provided on the SOI layer interposing a gate insulator; and a first elevated layer provided higher in height from the SOI layer than the gate electrode at both sidewall sides of the gate electrode on the SOI layer so as to constitute a source and drain. Further, there is also provided a bulk-MISFET including: a gate electrode provided on a silicon substrate interposing a gate insulator thicker than the gate insulator of the SOI MISFET; and a second elevated layer configuring a source and drain provided on a semiconductor substrate at both sidewalls of the gate electrode. A the first elevated layer is thicker than the elevated layer, and the whole of the gate electrodes, part of the source and drain of the SOI-MISFET, and part of the source and drain of the bulk-MISFET are silicided.

Abstract: An n well and a p well disposed at a predetermined interval on a main surface of a SOI substrate with a thin BOX layer are formed, and an nMIS formed on the p well has a pair of n-type source/drain regions formed on semiconductor layers stacked on a main surface of the SOI layer at a predetermined distance, a gate insulating film, a gate electrode and sidewalls sandwiched between the pair of n-type source/drain regions. A device isolation is formed between the n well and the p well, and a side edge portion of the device isolation extends toward a gate electrode side more than a side edge portion of the n-type source/drain region (sidewall of the BOX layer).

Abstract: Characteristics of a semiconductor device having a FINFET are improved. The FINFET has: a channel layer arranged in an arch shape on a semiconductor substrate and formed of monocrystalline silicon; a front gate electrode formed on a part of an outside of the channel layer through a front gate insulating film; and a back gate electrode formed so as to be buried inside the channel layer through a back gate insulating film. The back gate electrode arranged inside the arch shape is arranged so as to pass through the front gate electrode.

Abstract: A technique to be applied to a semiconductor device for achieving low power consumption by improving a shape at a boundary portion of a shallow trench and an SOI layer of an SOI substrate. A position (SOI edge) at which a main surface of a silicon substrate and a line extended along a side surface of an SOI layer are crossed is recessed away from a shallow-trench isolation more than a position (STI edge) at which a line extended along a sidewall of a shallow trench and a line extended along the main surface of the silicon substrate are crossed, and a corner of the silicon substrate at the STI edge has a curved surface.

Abstract: A semiconductor device and manufacturing method of the same is provided in which the driving current of a pMOSFET is increased, through a scheme formed easily using an existing silicon process. A pMOSFET is formed with a channel in a <100> direction on a (100) silicon substrate. A compressive stress is applied in a direction perpendicular to the channel by an STI.

Abstract: When a bulk silicon substrate and an SOI substrate are used separately, a board area is increased and so it is impossible to reduce the size of a semiconductor device as a whole. On the other hand, when an SOI-type MISFET and a bulk-type MISFET are formed on a same substrate, the SOI-type MISFET and the bulk-type MISFET should be formed in separate steps respectively, and thus the process gets complicated. A single crystal semiconductor substrate and an SOI substrate separated from the single crystal semiconductor substrate by a thin buried insulating film and having a thin single crystal semiconductor thin film (SOI layer) are used, and well diffusion layer regions, drain regions, gate insulating films and gate electrodes of the SOI-type MISFET and the bulk-type MISFET are formed in same steps. Since the bulk-type MISFET and the SOI-type MISFET can be formed on the same substrate, the board area can be reduced.

Abstract: Performance of a semiconductor device having a MIS transistor is improved. A semiconductor device includes: a pair of source/drain regions each formed by stacking a semiconductor layer on a main surface of a silicon substrate; a sidewall insulating film covering each sidewall of the source/drain regions; a gate electrode arranged so as to interpose a gate insulating film on the main surface of the silicon substrate at a position sandwiched by the sidewall insulating films in a plane; and extension regions formed to extend from a portion below and lateral to the gate electrode to a portion below and lateral to each of the source/drain regions, wherein a sidewall of the sidewall insulating film being adjacent to the gate insulating film and the gate electrode has an inclination of a forward tapered shape.

Abstract: A semiconductor device and manufacturing method of the same is provided in which the driving current of a pMOSFET is increased, through a scheme formed easily using an existing silicon process. A pMOSFET is formed with a channel in a <100> direction on a (100) silicon substrate. A compressive stress is applied in a direction perpendicular to the channel by an STI.

Abstract: Provided are a semiconductor device capable of improving the drive capacity of a MOS transistor even if the SOI layer is thinned; and a manufacturing method of the device. In a NMOS transistor formed in a NMOS formation region, a source/drain region is formed to penetrate through a buried oxide film and reach a threshold voltage controlling diffusion layer of a semiconductor substrate. In a PMOS transistor formed in a PMOS formation region, a source/drain region is formed to penetrate through a buried oxide film and reach a threshold voltage control diffusion layer of the semiconductor substrate.

Abstract: To provide a semiconductor device having a thin-film BOX-SOI structure and capable of realizing a high-speed operation of a logic circuit and a stable operation of a memory circuit. A semiconductor device according to the present invention includes a semiconductor support substrate, an insulation layer having a thickness of at mast 10 nm, and a semiconductor layer. In an upper surface of the semiconductor layer, a first field-effect transistor including a first gate electrode and constituting a logic circuit is formed. Further, in the upper surface of the semiconductor layer, a second field-effect transistor including a second gate electrode and constituting a memory circuit is formed. At least three well regions having different conductivity types are formed in the semiconductor support substrate.

Abstract: A semiconductor device and manufacturing method of the same is provided in which the driving current of a pMOSFET is increased, through a scheme formed easily using an existing silicon process. A pMOSFET is formed with a channel in a <100> direction on a (100) silicon substrate. A compressive stress is applied in a direction perpendicular to the channel by an STI.

Abstract: An object of the present invention is to provide a semiconductor device having a fin-type transistor that is excellent in characteristics by forming a fin-shaped semiconductor portion and a gate electrode with high precision or by making improvement regarding variations in characteristics among elements. The present invention is a semiconductor device including a fin-shaped semiconductor portion having a source region formed on one side thereof and a drain region formed on the other side thereof, and a gate electrode formed between the source region and the drain region to surround the fin-shaped semiconductor portion with a gate insulating film interposed therebetween. One solution for solving the problem according to the invention is that the gate electrode uses a metal material or a silicide material that is wet etchable.

Abstract: There is provided an SOI-MISFET including: an SOI layer; a gate electrode provided on the SOI layer interposing a gate insulator; and a first elevated layer provided higher in height from the SOI layer than the gate electrode at both sidewall sides of the gate electrode on the SOI layer so as to constitute a source and drain. Further, there is also provided a bulk-MISFET including: a gate electrode provided on a silicon substrate interposing a gate insulator thicker than the gate insulator of the SOI MISFET; and a second elevated layer configuring a source and drain provided on a semiconductor substrate at both sidewalls of the gate electrode. A the first elevated layer is thicker than the elevated layer, and the whole of the gate electrodes, part of the source and drain of the SOI-MISFET, and part of the source and drain of the bulk-MISFET are silicided.

Abstract: A CMOS circuit in low-voltage implementation, low power-consumption implementation, high-speed implementation, or small-size implementation. In a circuit which uses a FD-SOI MOST where a back gate is controlled by a well, voltage amplitude at the well is made larger than input-voltage amplitude at the gate. Alternatively, the circuit is modified into a circuit which uses a MOST that changes dynamically into an enhancement mode and a depletion mode.

Abstract: A semiconductor device having a passive element whose characteristic is adjustable even after manufacture by applying back bias voltage is provided. Formed on a main surface of a SOI substrate comprising a supporting substrate, a BOX layer, and an SOI layer is a MOS varactor comprising a gate dielectric formed on a surface of the SOI layer, a gate electrode formed on the gate dielectric, and a n+ type semiconductor region formed in the SOI layer located on both sides of the gate electrode. The MOS varactor, is configured so that capacitance formed by the SOI layer, gate dielectric, and gate electrode is varied by applying bias voltage to the supporting substrate (p type well) under the gate electrode.