Patents by Inventor Ryuta Tsuchiya
Ryuta Tsuchiya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080258218Abstract: A MIS transistor having an inclined stacked source/drain structure increased in speed is provided. The MIS transistor comprises: a gate electrode formed on a substrate; a first sidewall insulating film formed on the substrate and along a sidewall of the gate electrode; source/drain semiconductor regions formed on a main surface of the substrate and respectively having one edge positioned under the sidewall of the gate electrode; a first stacked layer formed on the source/drain semiconductor regions and in contact with the first sidewall insulating film; a second sidewall insulating film formed on the stacked layer and in contact with the first sidewall insulating film; and a second stacked layer formed on the first stacked layer and in contact with the second sidewall insulating layer.Type: ApplicationFiled: April 17, 2008Publication date: October 23, 2008Inventors: Yusuke Morita, Yoshinobu Kimura, Ryuta Tsuchiya, Nobuyuki Sugii, Shinichiro Kimura
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Patent number: 7385436Abstract: A CMOS circuit in low-voltage implementation, low power-consumption implementation, high-speed implementation, or small-size implementation. In a circuit which uses a FD-SOI MOST where a back gate is controlled by a well, voltage amplitude at the well is made larger than input-voltage amplitude at the gate. Alternatively, the circuit is modified into a circuit which uses a MOST that changes dynamically into an enhancement mode and a depletion mode.Type: GrantFiled: March 7, 2007Date of Patent: June 10, 2008Assignee: Hitachi, Ltd.Inventors: Kiyoo Itoh, Ryuta Tsuchiya, Takayuki Kawahara
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Publication number: 20080017904Abstract: A DRAM capable of realizing reduced power consumption, high-speed operation, and high reliability is provided. A gate electrode configuring a memory cell transistor of the DRAM is composed of an n-type polysilicon film and a W (tungsten) film stacked thereon. A part of the polysilicon film is embedded in a trench formed in a silicon substrate in order to elongate the effective channel length of the memory cell transistor. The other part of the polysilicon film is located above the trench, and an upper surface thereof is located above a surface of the silicon substrate (p-type well). Therefore, distances between the W film and a source and drain (n-type semiconductor regions) are ensured.Type: ApplicationFiled: July 6, 2007Publication date: January 24, 2008Inventors: Satoru AKIYAMA, Ryuta Tsuchiya, Tomonori Sekiguchi, Riichiro Takemura, Masayuki Nakamura, Yasushi Yamazaki, Shigeru Shiratake
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Publication number: 20070290264Abstract: The invention aims at increasing an effect of a strain applying technique for enhancing transistor performance in a fully depleted silicon-on-insulator (FDSOI) type transistor having a thin buried oxide (BOX) film. In an FDSOI type transistor having a very thin SOI structure (6), a stress generating region is formed on a back face side (5) of a very thin BOX layer (4) in order to apply strains to portions in which channels are intended to be formed. Desired portions on a back face side of the BOX layer (4) are amorphized by performing ion implantation, and are then recrystallized by performing a heat treatment in a state where a stress applying film (3) is formed, thereby transferring stresses from the stress applying film (3) to the portions in which the channels are intended to be formed. Thus, the stress generating region is formed.Type: ApplicationFiled: February 13, 2007Publication date: December 20, 2007Inventors: Nobuyuki Sugii, Ryuta Tsuchiya, Yusuke Morita
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Publication number: 20070284582Abstract: A semiconductor device and manufacturing method of the same is provided in which the driving current of a PMOSFET is increased, through a scheme formed easily using an existing silicon process. A PMOSFET is formed with a channel in a <100> direction on a (100) silicon substrate. A compressive stress is applied in a direction perpendicular to the channel by an STI.Type: ApplicationFiled: May 9, 2007Publication date: December 13, 2007Inventors: SHINICHI SAITO, Digh Hisamoto, Yoshinobu Kimura, Nobuyuki Sugii, Ryuta Tsuchiya
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Publication number: 20070266933Abstract: It is an object of the present invention to provide a method of manufacturing an SOI wafer at low cost and with high yield. It is another object of the present invention to provide a semiconductor device including also bulk type MISFETs used as high voltage regions and a method of manufacturing the same without using complicated processes and increasing the size of a semiconductor chip. The method of manufacturing a semiconductor device comprises selectively epitaxially growing a single-crystal Si layer and continuously performing the epitaxial growth without bringing a substrate temperature increased during the growth to room temperature even once. An epitaxially grown surface is then etched and planarized. The substrate temperature is then cooled down to the room temperature.Type: ApplicationFiled: May 18, 2007Publication date: November 22, 2007Inventors: Ryuta Tsuchiya, Yoshinobu Kimura, Yusuke Morita
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Publication number: 20070152736Abstract: A CMOS circuit in low-voltage implementation, low power-consumption implementation, high-speed implementation, or small-size implementation. In a circuit which uses a FD-SOI MOST where a back gate is controlled by a well, voltage amplitude at the well is made larger than input-voltage amplitude at the gate. Alternatively, the circuit is modified into a circuit which uses a MOST that changes dynamically into an enhancement mode and a depletion mode.Type: ApplicationFiled: March 7, 2007Publication date: July 5, 2007Inventors: Kiyoo Itoh, Ryuta Tsuchiya, Takayuki Kawahara
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Publication number: 20070008027Abstract: A CMOS circuit in low-voltage implementation, low power-consumption implementation, high-speed implementation, or small-size implementation. In a circuit which uses a FD-SOI MOST where a back gate is controlled by a well, voltage amplitude at the well is made larger than input-voltage amplitude at the gate. Alternatively, the circuit is modified into a circuit which uses a MOST that changes dynamically into an enhancement mode and a depletion mode.Type: ApplicationFiled: February 27, 2006Publication date: January 11, 2007Inventors: Kiyoo Itoh, Ryuta Tsuchiya, Takayuki Kawahara
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Patent number: 7049589Abstract: The present invention may include a pattern inspection method of extracting a pattern edge shape from an image obtained by a scanning microscope and inspecting the pattern. A control section and a computer of the scanning microscope process the intensity distribution of reflected electrons or secondary electrons, find the distribution of gate lengths in a single gate from data about edge positions, estimate the transistor performance by assuming a finally fabricated transistor to be a parallel connection of a plurality of transistors having various gate lengths, and determine the pattern quality and grade based on an estimated result. In this manner, it is possible to highly, accurately and quickly estimate an effect of edge roughness on the device performance and highly accurately and efficiently inspect patterns in accordance with device specifications.Type: GrantFiled: January 8, 2004Date of Patent: May 23, 2006Assignees: Hitachi, Ltd., Hitachi High-Technologies CorporationInventors: Atsuko Yamaguchi, Hiroshi Fukuda, Ryuta Tsuchiya, Hiroki Kawada, Shozo Yoneda
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Publication number: 20060081836Abstract: In a field effect semiconductor device for high frequency power amplification, it is difficult to achieve size reduction and increased efficiency simultaneously while ensuring voltage withstanding. A further improvement in efficiency is attained by using a strained Si channel for LDMOS at an output stage for high frequency power amplification. Further, the efficiency is improved as much as possible while decreasing a leak current, by optimizing the film thickness of the strained Si layer having a channel region, inactivation of defects and a field plate structure.Type: ApplicationFiled: October 14, 2005Publication date: April 20, 2006Inventors: Yoshinobu Kimura, Nobuyuki Sugii, Shinichiro Kimura, Ryuta Tsuchiya, Shinichi Saito
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Patent number: 7001818Abstract: By suppressing a short-channel effect of a MIS field-effect transistor and reducing a fringing capacitance of a gate, a signal delay in the transistor can be shortened. The MIS field-effect transistor is formed d by forming a side-wall spacer from a dielectric having a large dielectric constant and then forming an impurity diffusion layer area with the side-wall spacer used as an introduction end in an ion implantation process to introduce impurities. In this case, the side wall of the side-wall spacer having the large dielectric constant has an optimum film thickness in the range from 5 nm to 15 nm, which is required for achieving a large driving current. On the other hand, a side-wall spacer on an outer side is made of a silicon-dioxide film, which is a dielectric having a small dielectric constant.Type: GrantFiled: April 16, 2004Date of Patent: February 21, 2006Assignee: Hitachi, Ltd.Inventors: Ryuta Tsuchiya, Masatada Horiuchi
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Publication number: 20060001111Abstract: In a full depletion MISFET, there is a limit to control on a threshold voltage Vth by an impurity concentration in principle when a monocrystalline SOI layer becomes thin on the order of a few tens of nm. It was thus difficult to simultaneously realize predetermined Vth of both n and p types in a complementary MISFET. A gate insulating film for the MISFET is formed as a laminated layer of a metal oxide and an oxynitride. A gate electrode is formed using a polycrystalline Si semiconductor film of the same conductivity type as a source-drain. Predetermined Vth for enhancement are simultaneously achieved by a shift of a flatband voltage produced between the gate insulating film and the gate electrode made of the semiconductor film. Since a variation in Vth due to a statistical fluctuation in the number of impurities with respect to one MISFET can be reduced as compared with the case in which each Vth is controlled by the impurity concentration, Vth and a power supply voltage can both be set low.Type: ApplicationFiled: June 20, 2005Publication date: January 5, 2006Inventors: Ryuta Tsuchiya, Shinichi Sato, Masatada Horiuchi
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Publication number: 20050139867Abstract: The Mott transistor capable of operating at a room temperature can be realized by using a self-organized nanoparticle array for the channel portion. The nanoparticle used in the present invention comprises metal and organic molecules, and the size thereof is extremely small, that is, about a few nm. Therefore, the charging energy is sufficiently larger than the thermal energy kBT=26 meV, and the transistor can operate at a room temperature. Also, since the nanoparticles with a diameter of a few nm are arranged in a self-organized manner and the Mott transition can be caused by the change of a number of electrons of the surface density of about 1012 cm?2, the transistor can operate by the gate voltage of about several V.Type: ApplicationFiled: September 3, 2004Publication date: June 30, 2005Inventors: Shin-ichi Saito, Tadashi Arai, Digh Hisamoto, Ryuta Tsuchiya, Hiroshi Fukuda, Takahiro Onai
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Publication number: 20040207013Abstract: By suppressing a short-channel effect of a MIS field-effect transistor and reducing a fringing capacitance of a gate, a signal delay in the transistor can be shortened. The MIS field-effect transistor is formed d by forming a side-wall spacer from a dielectric having a large dielectric constant and then forming an impurity diffusion layer area with the side-wall spacer used as an introduction end in an ion implantation process to introduce impurities. In this case, the side wall of the side-wall spacer having the large dielectric constant has an optimum film thickness in the range from 5 nm to 15 nm, which is required for achieving a large driving current. On the other hand, a side-wall spacer on an outer side is made of a silicon-dioxide film, which is a dielectric having a small dielectric constant.Type: ApplicationFiled: April 16, 2004Publication date: October 21, 2004Applicant: Hitachi, Ltd.Inventors: Ryuta Tsuchiya, Masatada Horiuchi
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Publication number: 20040195507Abstract: The present invention may include a pattern inspection method of extracting a pattern edge shape from an image obtained by a scanning microscope and inspecting the pattern. A control section and a computer of the scanning microscope process the intensity distribution of reflected electrons or secondary electrons, find the distribution of gate lengths in a single gate from data about edge positions, estimate the transistor performance by assuming a finally fabricated transistor to be a parallel connection of a plurality of transistors having various gate lengths, and determine the pattern quality and grade based on an estimated result. In this manner, it is possible to highly, accurately and quickly estimate an effect of edge roughness on the device performance and highly accurately and efficiently inspect patterns in accordance with device specifications.Type: ApplicationFiled: January 8, 2004Publication date: October 7, 2004Inventors: Atsuko Yamaguchi, Hiroshi Fukuda, Ryuta Tsuchiya, Hiroki Kawada, Shozo Yoneda
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Patent number: 6744099Abstract: By suppressing a short-channel effect of a MIS field-effect transistor and reducing a fringing capacitance of a gate, a signal delay in the transistor can be shortened. The MIS field-effect transistor is formed d by forming a side-wall spacer from a dielectric having a large dielectric constant and then forming an impurity diffusion layer area with the side-wall spacer used as an introduction end in an ion implantation process to introduce impurities. In this case, the side wall of the side-wall spacer having the large dielectric constant has an optimum film thickness in the range from 5 nm to 15 nm, which is required for achieving a large driving current. On the other hand, a side-wall spacer on an outer side is made of a silicon-dioxide film, which is a dielectric having a small dielectric constant.Type: GrantFiled: February 25, 2003Date of Patent: June 1, 2004Assignee: Hitachi, Ltd.Inventors: Ryuta Tsuchiya, Masatada Horiuchi
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Patent number: 6667199Abstract: The present invention provides a MISFET with a replacement gate electrode, which ensures large ON-current. A semiconductor device, in which on the substrate, first and second field effect transistors are formed, the first field effect transistor is a replacement gate type field effect transistor, and the length of the overlap between a gate electrode and a source/drain diffusion zone of the first field effect transistor correspond to that between a gate electrode and a source/drain diffusion zone of the second field effect transistor.Type: GrantFiled: February 25, 2002Date of Patent: December 23, 2003Assignee: Hitachi, Ltd.Inventors: Kazuyoshi Torii, Ryuta Tsuchiya, Masatada Horiuchi, Takahiro Onai
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Publication number: 20030218214Abstract: By suppressing a short-channel effect of a MIS field-effect transistor and reducing a fringing capacitance of a gate, a signal delay in the transistor can be shortened. The MIS field-effect transistor is formed d by forming a side-wall spacer from a dielectric having a large dielectric constant and then forming an impurity diffusion layer area with the side-wall spacer used as an introduction end in an ion implantation process to introduce impurities. In this case, the side wall of the side-wall spacer having the large dielectric constant has an optimum film thickness in the range from 5 nm to 15 nm, which is required for achieving a large driving current. On the other hand, a side-wall spacer on an outer side is made of a silicon-dioxide film, which is a dielectric having a small dielectric constant.Type: ApplicationFiled: February 25, 2003Publication date: November 27, 2003Inventors: Ryuta Tsuchiya, Masatada Horiuchi
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Publication number: 20030022422Abstract: The present invention provides a MISFET with a replacement gate electrode, which ensures large ON-current.Type: ApplicationFiled: February 25, 2002Publication date: January 30, 2003Inventors: Kazuyoshi Torii, Ryuta Tsuchiya, Masatada Horiuchi, Takahiro Onai