Abstract: A digital signal processor capable of performing a Viterbi algorithm is provided. The digital signal processor includes an instruction fetching unit that fetches instructions; a decoding unit that decodes the instructions fetched by the instruction fetching unit, and an execution unit that executes the instructions decoded by the decoding unit. The execution unit includes a first comparing unit that compares first data with second data and a second comparing unit that compares third data with fourth data. The first comparing unit and the second comparing unit operate in parallel. Also, the first data, the second data, the third data, and the fourth data can each be one of four results obtained by adding one of two path metrics to one of two branch metrics. The execution unit outputs any two new path metrics in a high order position and a low order position respectively.

Abstract: Memory address generation apparatus 12 generates memory addresses, multiplier 15 reads from memory 14 storing row transposition patterns of a matrix a row transposition pattern value corresponding to the row number outputfrom row counter 11 and calculates an address offset value by multiplying the transposition pattern value of the read row by the number of columns of the matrix, adder 16 reads from memory 13 storing row transposition patterns of the matrix a column transposition pattern value corresponding to the memory address generated by the memory address generation apparatus and generates an interleave address by adding up the transposition pattern value of the read column and the address offset value.

Abstract: A method of operating a digital signal processor is provided. The digital signal processor may be provided as a radio communication mobile station, a radio communication base station apparatus, or a CDMA radio communication system. Each path metric PM1 and PM0 of an old state is added to each branch metric BM1 and BM0 separately. A path metric of a new state N is formed by comparing the value of PM1+BM1 to the value of PM0+BM0. A path metric of a new state N+2k−2 is formed by comparing the value of PM1+BM0 to PM0+BM1.

Abstract: Correction circuit 102 multiplies data subject to Rake combining from among data of a plurality of channels output from storage section 101 by correction coefficients and outputs the channel data to Rake section 103. Correction circuit 102 then multiplies the data of channels other than the channels subject to Rake combining by “0” and outputs the other channel data to Rake section 103. The value of the other channel data multiplied by “0” becomes “0” having no effect on the addition result of Rake combining. Rake section 103 applies a complex addition to the data output from correction circuit 102 and outputs the addition result to DSP 105.

Abstract: A method of operating a digital signal processor is provided. The digital signal processor may be provided as a radio communication mobile station, a radio communication base station apparatus, or a CDMA radio communication system. Each path metric PM1 and PM0 of an old state is added to each branch metric BM1 and BM0 separately. A path metric of a new state N is formed by comparing the value of PM1+BM1 to the value of PM0+BM0. A path metric of a new state N+2k−2 is formed by comparing the value of PM1+BM0 to PM0+BM1.

Abstract: Two path metrics (PM0, PM1) are read from path metric storing means 1, and two path metrics (BM0, BM1) are read from branch metric storing means 3. An ACS operation is executed using PM0+MB0 and PM1+BM1 by comparing means 5, adding means 6, comparison result storing means 7, and selecting means 8. In parallel with the ACS operation, an ACS operation is executed using PM0+MB1 and PM1+BM0 by comparing means 9, adding means 10, comparison result storing means 11, and selecting means 12.

Abstract: In a binary fixed-point number system in which the most significant bit is a sign bit and the decimal point is between the most significant bit and a bit which is lower by one bit than the most significant bit, the circuit scale for digit place aligning means is reduced and a double-precision multiplication with an excellent efficiency is realized. Products of the high-order word/low-order word of a double-precision multiplicand and the high-order word/low-order word of a double-precision multiplier are obtained by using a single-precision multiplying device. A digit place alignment addition operation is performed on the obtained products to produce a double-precision multiplication result.