Patents by Inventor Sèbastien Kerdiles

Sèbastien Kerdiles has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110233720
    Abstract: A method and/or system are provided for producing a structure comprising a thin layer of semiconductor material on a substrate. The method includes creating an area of embrittlement in the thickness of a donor substrate, bonding the donor substrate with a support substrate and detaching the donor substrate at the level of the area of embrittlement to transfer a thin layer of the donor substrate onto the support substrate. The method also includes thermal treatment of this resulting structure to stabilize the bonding interface between the thin layer and the substrate support. The invention also relates to the structures obtained by such a process.
    Type: Application
    Filed: June 6, 2011
    Publication date: September 29, 2011
    Applicant: S.O.I.TEC Silicon on Insulator Technologies
    Inventors: Eric Neyret, Sebastien Kerdiles
  • Patent number: 8003493
    Abstract: A process for splitting a semiconductor substrate having an identification notch on its periphery, by creating a weakened zone in the substrate by implanting atomic species into the substrate while the substrate is held in place on a portion of its periphery during the implanting; and splitting the substrate along the weakened zone by placing the held portion of the substrate in a splitting-wave initiation sector while positioning the notch for initiating a splitting wave followed by the propagation of the wave into the substrate. During splitting the notch is positioned so that it is in a quarter of the periphery of the substrate diametrically opposite the sector for initiating the splitting wave or in the quarter of the periphery of the substrate that is centered on the sector.
    Type: Grant
    Filed: October 21, 2008
    Date of Patent: August 23, 2011
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Nadia Ben Mohamed, Sébastien Kerdiles
  • Patent number: 7977747
    Abstract: The invention specifically relates to methods of fabricating a composite substrate by providing a first insulating layer on a support substrate at a thickness of e1 and providing a second insulating layer on a source substrate at a thickness of e2, with each layer having an exposed face for bonding; providing plasma activation energy in an amount sufficient to activate a portion of the thickness of the face of the first insulating layer emp1 and a portion of the thickness of the face of the second insulating layer emp1; providing a final insulating layer by molecular bonding the activated face of the first insulating layer with the activated face of the second insulating layer; and removing a back portion of the source substrate while retaining an active layer comprising a remaining portion of the source substrate bonded to the support substrate with the final insulating layer interposed therein to form the composite substrate.
    Type: Grant
    Filed: February 18, 2010
    Date of Patent: July 12, 2011
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Frédéric Allibert, Sébastien Kerdiles
  • Patent number: 7972939
    Abstract: A method for minimizing or avoiding contamination of a receiving handle wafer during transfer of a thin layer from a donor wafer. This method includes providing a donor wafer and a receiving handle wafer, each having a first surface prepared for bonding and a second surface, with the donor wafer providing a layer of material to be transferred to the receiving handle wafer. Next, at least one of the first surfaces is treated to provide increased bonding energy when the first surfaces are bonded together; the surfaces are then bonded together to form an intermediate multilayer structure; and a portion of the donor wafer is removed to transfer the thin layer to the receiving handle wafer and form the semiconductor structure. This method avoids or minimizes contamination of the second surface of the receiving handle wafer by treating only the first surface of the donor wafer prior to bonding by exposure to a plasma, and by conducting any thermal treatments after plasma activation at a temperature of 300° C.
    Type: Grant
    Filed: September 24, 2009
    Date of Patent: July 5, 2011
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Sébastien Kerdiles, Christophe Maleville, Fabrice Letertre, Olivier Rayssac
  • Publication number: 20110140244
    Abstract: The invention relates to a method for routing a chamfered substrate, having applications in the field of electronics, optics, or optoelectronics, which involves depositing a layer of a protective material on a peripheral annular zone of the substrate preferably with the aid of a plasma, partially etching the protective material with the aid of a plasma, so as to preserve a protective ring of the deposited material on the front face of the substrate, this ring located at a distance from the edge of the substrate, so as to delimit an accessible peripheral annular zone, etching a thickness of the material constituting the substrate to be routed, preferably with the aid of a plasma that is level with the accessible peripheral annular zone of the substrate, and removing the ring of protective material preferably with the aid of a plasma.
    Type: Application
    Filed: December 10, 2010
    Publication date: June 16, 2011
    Inventors: Walter Schwarzenbach, Aziz Alami-Idrissi, Alexandre Chibko, Sébastien Kerdiles
  • Patent number: 7892951
    Abstract: A method of producing a semiconductor structure having a buried insulating layer having a thickness between 2 and 25 nm, by: forming at least one insulating layer on a surface of a first or second substrate, or both, wherein the surfaces are free from an insulator or presenting a native oxide layer resulting from exposure of the substrates to ambient conditions; assembling the first and second substrates; and thinning down the first substrate, in order to obtain the semiconductor structure. In this method, the insulating layer forming stage is a plasma activation based on an oxidizing or nitriding gas.
    Type: Grant
    Filed: September 24, 2008
    Date of Patent: February 22, 2011
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Didier Landru, Sébastien Kerdiles
  • Patent number: 7863158
    Abstract: A method and/or system are provided for producing a structure comprising a thin layer of semiconductor material on a substrate. The method includes creating an area of embrittlement in the thickness of a donor substrate, bonding the donor substrate with a support substrate and detaching the donor substrate at the level of the area of embrittlement to transfer a thin layer of the donor substrate onto the support substrate. The method also includes thermal treatment of this resulting structure to stabilize the bonding interface between the thin layer and the substrate support. The invention also relates to the structures obtained by such a process.
    Type: Grant
    Filed: May 29, 2007
    Date of Patent: January 4, 2011
    Assignee: S.O.I.TEC Silicon on Insulator Technologies
    Inventors: Eric Neyret, Sebastien Kerdiles
  • Publication number: 20100323496
    Abstract: The invention relates to a process for manufacturing a composite substrate comprising bonding a first substrate (10) onto a second semi-conducting substrate (30), characterized in that it includes, before bonding, the formation of a bonding layer (20) between the first and the second substrate, the bonding layer (20) comprising a plurality of islands (21) distributed over the surface of the first substrate (10) in a determined pattern and separated from one another by regions (22) of a different type, which are distributed in a complementary pattern, wherein the islands (21) are formed via a plasma treatment of the material of the first substrate (10).
    Type: Application
    Filed: March 26, 2008
    Publication date: December 23, 2010
    Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
    Inventors: Frederic Allibert, Sebastien Kerdiles
  • Publication number: 20100304507
    Abstract: The invention relates to a method of producing a semiconductor structure by transferring a layer of a donor substrate to a receiver substrate, with the creation of an embrittlement zone in the donor substrate to define the transfer layer, and the treatment of the surface of one of the substrates to increase the bonding strength between them, followed by the direct wafer bonding of the substrates and the detachment of the donor substrate at the embrittlement zone to form the semiconductor structure, in which the surface of the receiver substrate, except for a peripheral crown, is covered with the transferred layer. The treatment of the substrate surface is controlled so that the bonding strength between the substrates is lower in a peripheral area than in a central area. The peripheral area has a width at least equal to the that of the crown and less than 10 mm.
    Type: Application
    Filed: September 11, 2008
    Publication date: December 2, 2010
    Applicant: S.O.I. Tec Silicon on Insulator Technologies
    Inventors: Brigitte Soulier Bouchet, Sébastien Kerdiles, Walter Schwarzenbach
  • Publication number: 20100200854
    Abstract: A method for reclaiming a surface of a substrate, wherein the surface, in particular a silicon surface, comprises a protruding residual topography, comprising at least the layer of a first material. By providing a filling material in the non-protruding areas of the surface of the substrate and the subsequent polishing, the reclaiming can be carried out such that the material consuming double-sided polishing step used in the prior art is no longer necessary.
    Type: Application
    Filed: February 12, 2010
    Publication date: August 12, 2010
    Applicant: S.O.I.TEC Silicon on Insulator Technologies
    Inventors: Aziz Alami-Idrissi, Sebastien Kerdiles, Walter Schwarzenbach
  • Publication number: 20100190416
    Abstract: Disclosed are devices and methods for chemical and mechanical polishing of the edge of a semiconductor substrate that includes a protruding residual topography in a peripheral region of the substrate resulting from a layer transfer process based on an ion implantation step, a bonding step and a detachment step, such as Smart-Cut™. To be able to remove this step-like region, exemplary devices include a polishing pad, wherein the polishing pad is arranged and configured such that its cross section in a plane perpendicular to the surface of a substrate holder is curved. The disclosure furthermore relates to a pad holder used certain exemplary devices and methods for polishing a semiconductor substrate that has a protruding residual topography.
    Type: Application
    Filed: January 28, 2010
    Publication date: July 29, 2010
    Applicant: S.O.I.TEC Silicon on Insulator Technologies
    Inventors: Walter Schwarzenbach, Sebastien Kerdiles, Aziz Alami-Idrissi
  • Publication number: 20100187649
    Abstract: The present invention relates to a process for preparing semiconductor on insulator type structures that include a semiconductor layer of a donor substrate, an insulator layer and a receiver substrate. The process includes bonding of the donor substrate onto the receiver substrate, with at least one of the substrates being coated with an insulator layer, and forming at the bonding interface a so-called trapping interface of electrically active traps suitable for retaining charge carriers. The invention also relates to a semiconductor on insulator type structure that includes such a trapping interface.
    Type: Application
    Filed: July 21, 2008
    Publication date: July 29, 2010
    Inventors: Frédéric Allibert, Sébastien Kerdiles
  • Publication number: 20100176493
    Abstract: A process for splitting a semiconductor substrate having an identification notch on its periphery, by creating a weakened zone in the substrate by implanting atomic species into the substrate while the substrate is held in place on a portion of its periphery during the implanting; and splitting the substrate along the weakened zone by placing the held portion of the substrate in a splitting-wave initiation sector while positioning the notch for initiating a splitting wave followed by the propagation of the wave into the substrate. During splitting the notch is positioned so that it is in a quarter of the periphery of the substrate diametrically opposite the sector for initiating the splitting wave or in the quarter of the periphery of the substrate that is centered on the sector.
    Type: Application
    Filed: October 21, 2008
    Publication date: July 15, 2010
    Inventors: Nadia Ben Mohamed, Sébastien Kerdiles
  • Patent number: 7740735
    Abstract: A tool and method for disuniting two wafers, wherein at least one of the wafers is used in fabricating substrates for microelectronics, optoelectronics, or optics. The method includes the steps of temporarily affixing two gripper members to respective opposite faces of the wafers; and sufficiently displacing one of the gripper members relative to the other for inducing controlled flexing in at least one of the members and for exerting a force close to one edge of the wafers to assist in disuniting the wafers. If desired, the bonding energy between two wafers can be determined by measuring the force exerted during the displacement step or measuring the separation of the wafers while performing the disuniting operation.
    Type: Grant
    Filed: December 6, 2006
    Date of Patent: June 22, 2010
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Sebastien Kerdiles, Yves-Matthieu Le Vaillant
  • Publication number: 20100148322
    Abstract: The invention specifically relates to methods of fabricating a composite substrate by providing a first insulating layer on a support substrate at a thickness of e1 and providing a second insulating layer on a source substrate at a thickness of e2, with each layer having an exposed face for bonding; providing plasma activation energy in an amount sufficient to activate a portion of the thickness of the face of the first insulating layer emp1 and a portion of the thickness of the face of the second insulating layer emp1; providing a final insulating layer by molecular bonding the activated face of the first insulating layer with the activated face of the second insulating layer; and removing a back portion of the source substrate while retaining an active layer comprising a remaining portion of the source substrate bonded to the support substrate with the final insulating layer interposed therein to form the composite substrate.
    Type: Application
    Filed: February 18, 2010
    Publication date: June 17, 2010
    Inventors: Frédéric Allibert, Sébastien Kerdiles
  • Patent number: 7736993
    Abstract: The invention specifically relates to methods of fabricating a composite substrate by providing a first insulating layer on a support substrate at a thickness of e1 and providing a second insulating layer on a source substrate at a thickness of e2, with each layer having an exposed face for bonding; providing plasma activation energy in an amount sufficient to activate a portion of the thickness of the face of the first insulating layer emp1 and a portion of the thickness of the face of the second insulating layer emp1; providing a final insulating layer by molecular bonding the activated face of the first insulating layer with the activated face of the second insulating layer; and removing a back portion of the source substrate while retaining an active layer comprising a remaining portion of the source substrate bonded to the support substrate with the final insulating layer interposed therein to form the composite substrate.
    Type: Grant
    Filed: June 23, 2006
    Date of Patent: June 15, 2010
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Frédéric Allibert, Sébastien Kerdiles
  • Publication number: 20100093152
    Abstract: The invention relates to a method of forming a structure comprising a thin layer of semiconductor material transferred from a donor substrate onto a second substrate, wherein two different atomic species are co-implanted under certain conditions into the donor substrate so as to create a weakened zone delimiting the thin layer to be transferred. The two different atomic species are implanted so that their peaks have an offset of less than 200 ? in the donor substrate, and the substrates are bonded together after roughening at least one of the bonding surfaces.
    Type: Application
    Filed: November 23, 2007
    Publication date: April 15, 2010
    Inventors: Sébastien Kerdiles, Willy Michel, Walter Schwarzenbach, Daniel Delprat, Nadia Ben Mohamed
  • Patent number: 7645682
    Abstract: The invention relates to improvements in a method for molecularly bonding first and second substrates together by placing them in surface to surface contact. The improvement includes, prior to placing the substrates in contact, cleaning the surface of one or both of the substrates in a manner to provide a cleaned surface that is slightly roughened compared to a conventionally polished surface, and heating at least one or both of the substrates prior to placing the substrates in contact while retaining the heating at least until the substrates are in surface to surface contact.
    Type: Grant
    Filed: October 16, 2007
    Date of Patent: January 12, 2010
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Sebastien Kerdiles, Willy Michel, Walter Schwarzenbach, Daniel Delprat
  • Publication number: 20090294072
    Abstract: The invention relates to equipment for carrying out a process for bonding by molecular adhesion of two substrates to one another during which the surfaces of the substrates are placed in close contact and bonding occurs by propagation of a bonding front between the substrates. The invention includes, prior to bonding, a step of modifying the surface state of one or both of the surfaces of the substrates so as to regulate the propagation speed of the bonding front. The surface can be modified by locally or uniformly heating or roughening the surface(s) of the substrate(s).
    Type: Application
    Filed: June 23, 2009
    Publication date: December 3, 2009
    Inventors: Sebastien Kerdiles, Carine Duret, Alexandre Vaufredaz, Frédéric Metral
  • Patent number: 7615464
    Abstract: A method for minimizing or avoiding contamination of a receiving handle wafer during transfer of a thin layer from a donor wafer. This method includes one step of providing a donor wafer and a receiving handle wafer, each having a first surface prepared for bonding and a second surface, with the donor layer including a zone of weakness that defines a thin layer of donor wafer material to be transferred to the receiving handle wafer. Next, at least one of the first surfaces is treated to provide increased bonding energy when the first surfaces are bonded together; the surfaces are then bonded together to form an intermediate multilayer structure; and the thin layer is transferred to the receiving handle wafer to form a final multilayer structure by detachment at the zone of weakness and removal of remaining material of the donor wafer.
    Type: Grant
    Filed: May 25, 2005
    Date of Patent: November 10, 2009
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Sébastien Kerdiles, Christophe Maleville, Fabrice Letertre, Olivier Rayssac