Patents by Inventor S. Chiang
S. Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5834824Abstract: A novel antifuse includes a composite of conductive particles dispersed throughout a nonconductive matrix, which composite is located inside an antifuse via. The antifuse via is defined by a dielectric layer that separates two electrodes. The electrodes can be located in the same conductive layer plane (typically parallel to and isolated from one another) or in two different conductive planes (typically formed transverse to one another and separated by a dielectric with an antifuse via formed therein). The electrodes can be coupled to, for example, active or passive regions of the integrated circuit. One embodiment of an antifuse (also called "composite antifuse") has only the composite in an antifuse via between the two conductive layers. Another embodiment of an antifuse (also called "hybrid antifuse") includes in addition to the composite, one or more thin dielectric layers also located in the antifuse via between the two conductive layers.Type: GrantFiled: March 14, 1995Date of Patent: November 10, 1998Assignee: Prolinx Labs CorporationInventors: William H. Shepherd, Steve S. Chiang, John Y. Xie
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Patent number: 5825072Abstract: A static-charge protection device for an antifuse includes an additional second-sized aperture smaller in area than the antifuse apertures disposed in the same inter-electrode dielectric layer. Antifuse material is disposed in the second-sized aperture, and the upper electrode extends over the second aperture as well as the first aperture. A preferred process for fabricating the protection device utilizes the step of forming the smaller apertures and forming their antifuse material layers simultaneously with forming the antifuse apertures.A static-charge protection device for an antifuse device includes an additional second-sized aperture larger in area than the first-sized antifuse apertures. Metal plug material is deposited and etched back. A layer of amorphous silicon antifuse material is formed and defined over the first and second sized apertures, the portion formed over the larger partially filled antifuse protection device cell being thinner.Type: GrantFiled: February 14, 1996Date of Patent: October 20, 1998Assignee: Actel CorporationInventors: Yeochung Yen, Wenn-Jei Chen, Steve S. Chiang, Abdul Rahim Forouhi
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Patent number: 5813881Abstract: Two types of programmable elements, fuses and antifuses, are disclosed for forming an electrically programmable cable in one embodiment and a cable adapter in another embodiment. The cable and the cable adapter can be used for interconnecting a cable connector of a first configuration to a cable connector of a second configuration.Type: GrantFiled: October 7, 1994Date of Patent: September 29, 1998Assignee: Prolinx Labs CorporationInventors: Richard J. Nathan, James J. D. Lan, Steve S. Chiang
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Patent number: 5808351Abstract: Two types of programmable elements, fuses and antifuses, are disclosed for forming an electrically programmable burn-in board in one embodiment and an electrically programmable device-under-test (DUT) card in another embodiment. Both types of programmable elements can also be used in a reconfiguration device for interconnecting electrical contacts in a first configuration to electrical contacts in a second configuration. The various embodiments of this invention include, for example, a component socket, a socket adapter, a cable, a cable adapter, a scrambler card for a burn-in board and a device-under-test card for a burn-in board. A method for forming a fuse is also disclosed.Type: GrantFiled: October 7, 1994Date of Patent: September 15, 1998Assignee: Prolinx Labs CorporationInventors: Richard J. Nathan, James J. D. Lan, Steve S. Chiang, William H. Shepherd
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Patent number: 5767575Abstract: An integrated circuit (IC) package substrate has a dielectric layer and a micro filled via formed substantially in the center of a hole in the dielectric layer. The IC package substrate has at least one chip bonding pad and one ball attach pad that are electrically coupled to each other by the micro filled via. The micro filled via is formed of a material called a "micro filled via material" that includes a binding material and optionally includes a number of particles (between 0%-90% by volume) dispersed in the binding material. The binding material can be any material, such as a polymer that is either conductive or nonconductive. The particles can be formed of any conductive material, such as a conductive polymer or a conductive metal (e.g. copper or gold). An electrical conductor can be originally formed simply by contact between conductive particles located adjacent to each other.Type: GrantFiled: October 17, 1995Date of Patent: June 16, 1998Assignee: Prolinx Labs CorporationInventors: James J. D. Lan, Steve S. Chiang, Paul Y. F. Wu, William H. Shepherd, John Y. Xie, Hang Jiang
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Patent number: 5726482Abstract: A device-under-test card includes a matrix of fuses and/or antifuses formed as part of a multi-layered structure. The matrix of fuses and/or antifuses can be electrically programmed to connect any one of first electrical contacts to any one of second electrical contacts and so allows the device-under-test card to act as a junction between burn-in board traces couplable to signal drivers and/or receivers and burn-in board traces couplable to terminals of a device-under-test. The device-under-test card also includes a discrete resistor or alternatively a resistor ladder that permits a terminal of a device-under-test to be coupled to a power or ground terminal or to any combination of resistances including a short, in addition or as an alternative to any one of various signal drivers and/or receivers.Type: GrantFiled: October 7, 1994Date of Patent: March 10, 1998Assignee: Prolinx Labs CorporationInventors: Richard J. Nathan, James J. D. Lan, Steve S. Chiang, Paul Y. F. Wu, Robert Osann, Jr.
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Patent number: 5572409Abstract: Two types of programmable elements, fuses and antifuses, are disclosed for forming an electrically programmable socket adapter in one embodiment. The socket adapter can be used for interconnecting an electronic component having terminals in a first configuration to electrical contacts in printed circuit board.Type: GrantFiled: October 7, 1994Date of Patent: November 5, 1996Assignee: Prolinx Labs CorporationInventors: Richard J. Nathan, James J. D. Lan, Steve S. Chiang
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Patent number: 5537108Abstract: A programming method in accordance with this invention partitions traces of a fuse matrix into groups wherein each group contains traces connected to fuses that are to remain intact. All of the traces in a group are connected to a first voltage so that the fuses between traces in the group are subjected to minimal currents. In one embodiment, all of the traces that are not in the group connected to the first voltage are connected to a second voltage such that a programming current passes through fuses to be programmed. In an alternative embodiment, traces in a second group are connected to the second voltage and all of the remaining traces are shorted to each other.Type: GrantFiled: October 7, 1994Date of Patent: July 16, 1996Assignee: Prolinx Labs CorporationInventors: Richard J. Nathan, James J. D. Lan, Steve S. Chiang, Paul Y. F. Wu
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Patent number: 5525830Abstract: According to the present invention, planar layers of Nitride (first nitride layer), a-Si (first a-Si layer), Nitride (second Nitride layer) and a-Si (second a-Si layer) are laid down over a first metallization layer. A dielectric layer is then laid down on top of the second a-Si layer. A via is opened in the dielectric layer with an etch gas which attacks a small portion of the second a-Si layer which, in effect, serves as a sacrificial etch-stop layer. A titanium layer is laid down over the via and allowed to thermally react with the remainder of the second a-Si layer to form an electrically conductive titanium silicide region in the area of the via the thickness of the second a-Si layer. The reaction is self-limiting and stops at the second Nitride layer. Subsequently a second metallization layer is disposed over the via.Type: GrantFiled: October 12, 1994Date of Patent: June 11, 1996Assignee: Actel CorporationInventors: Wenn-Jei Chen, Steve S. Chiang, Frank W. Hawley
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Patent number: 5519248Abstract: A static-charge protection device for an antifuse includes an additional second-sized aperture smaller in area than the antifuse apertures disposed in the same inter-electrode dielectric layer. Antifuse material is disposed in the second-sized aperture, and the upper electrode extends over the second aperture as well as the first aperture. A preferred process for fabricating the protection device utilizes the step of forming the smaller apertures and forming their antifuse material layers simultaneously with forming the antifuse apertures. A static-charge protection device for an antifuse device includes an additional second-sized aperture larger in area than the first-sized antifuse apertures. Metal plug material is deposited and etched back. A layer of amorphous silicon antifuse material is formed and defined over the first and second sized apertures, the portion formed over the larger partially filled antifuse protection device cell being thinner.Type: GrantFiled: July 19, 1994Date of Patent: May 21, 1996Assignee: Actel CorporationInventors: Yeouchung Yan, Wenn-Jei Chen, Steve S. Chiang, Abdul R. Forouhi
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Patent number: 5510730Abstract: A user-programmable interconnect architecture, which may be used for logic arrays for digital and analog system design, is disclosed. In one embodiment, a plurality of logic cells or modules in a matrix are connected by vertical and horizontal wiring channels. The wiring channels may in turn be programmed by the user to interconnect the various logic cells to implement the required logic function. The wiring channels comprise wiring segments connected by normally open reconfigurable programmable elements situated at the intersection of any two segments to be connected.Type: GrantFiled: June 21, 1995Date of Patent: April 23, 1996Assignee: Actel CorporationInventors: Abbas El Gamal, Steve S. S. Chiang
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Patent number: 5485031Abstract: The present invention relates to a high performance, high reliability antifuse using conductive electrodes. The problem of switch-off of the programmed antifuses is solved by reducing the thermal conductivity of the conductive electrodes. This is achieved by using lower thermal conductivity conductors for the electrodes or by using thinner electrodes to increase thermal resistance. According to a first aspect of the present invention, the problem of switch-off in conductor-to-conductor antifuses is solved by utilizing conductive electrode materials having a relatively lower thermal conductivity than prior art electrode materials. According to a second aspect of the present invention, the problem of switch-off in conductor-to-conductor antifuses is solved by utilizing relatively thin electrodes, thus increasing their thermal resistance.Type: GrantFiled: November 22, 1993Date of Patent: January 16, 1996Assignee: Actel CorporationInventors: Guobiao Zhang, Chenming Hu, Steve S. Chiang
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Patent number: 5460048Abstract: An ultrasonic sensor having a polarization maintaining fibre including two orthogonal linear principal axes and a straight sensing portion. A laser source directs a beam through a quarter wave plate to provide a circularly polarized beam to an input end of the fibre. The beam emerging from an output end of the fibre is directed to a linear polarizer and the intensity of the beam is detected by a photodetector. A signal processor thereafter generates suitable driving signals for a display unit indicative of mode coupling induced in the fibre by incident ultrasonic waves.Type: GrantFiled: August 18, 1992Date of Patent: October 24, 1995Inventors: Kin S. Chiang, Helen L. W. Chan
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Patent number: 5449947Abstract: A "read-disturb" resistant metal-to-metal antifuse includes a lower electrode comprising a first metal layer in a microcircuit structure. An inter-metal dielectric is disposed over the lower electrode and includes an antifuse aperture disposed therein. A first layer of antifuse material is disposed over exposed surface of the lower electrode in the antifuse aperture. A highly conductive layer is disposed over the first region of antifuse material and a second layer of antifuse material is disposed over the highly conductive layer. An upper electrode comprises a second metal layer disposed over the second layer of antifuse material. The first and second layers of antifuse material may comprise single-layer or multi-layer dielectric materials, amorphous silicon, or combinations of these materials.Type: GrantFiled: July 7, 1993Date of Patent: September 12, 1995Assignee: Actel CorporationInventors: Wenn-Jei Chen, Steve S. Chiang, Esam Elashmawi
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Patent number: 5412244Abstract: Electrically-programmable low-impedance antifuses are disclosed having capacitor-like structure with very low leakage before programming and a low resistance after programming. The antifuses of the present invention include a first conductive electrode which may be formed as a diffusion region in a semiconductor substrate or may be formed from a semiconductor material, such as polysilicon, located above and insulated from the substrate. A dielectric layer is disposed over the first electrode. A second electrode is formed over the dielectric layer from a semiconductor material such as polysilicon, or metal having a barrier metal underneath. At least one of the two electrodes of each antifuse is highly-doped or implanted with arsenic such that high concentrations of arsenic exist at the interface between the electrode and the dielectric layer.Type: GrantFiled: April 29, 1993Date of Patent: May 2, 1995Assignee: Actel CorporationInventors: Esmat Z. Hamdy, Amr M. Mohsen, John L. McCollum, Shih-Ou Chen, Steve S. Chiang
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Patent number: 5381035Abstract: According to the present invention, planar layers of Nitride (first nitride layer), a-Si (first a-Si layer), Nitride (second Nitride layer) and a-Si (second a-Si layer) are laid down over a first metallization layer. A dielectric layer is then laid down on top of the second a-Si layer. A via is opened in the dielectric layer with an etch gas which attacks a small portion of the second a-Si layer which, in effect, serves as a sacrificial etch-stop layer. A titanium layer is laid down over the via and allowed to thermally react with the remainder of the second a-Si layer to form an electrically conductive titanium silicide region in the area of the via the thickness of the second a-Si layer. The reaction is self-limiting and stops at the second Nitride layer. Subsequently a second metallization layer is disposed over the via.Type: GrantFiled: December 21, 1993Date of Patent: January 10, 1995Inventors: Wenn-Jei Chen, Steve S. Chiang, Frank W. Hawley
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Patent number: 5369054Abstract: A static-charge protection device for an antifuse includes an additional second-sized aperture smaller in area than the antifuse apertures disposed in the same inter-electrode dielectric layer. Antifuse material is disposed in the second-sized aperture, and the upper electrode extends over the second aperture as well as the first aperture. A preferred process for fabricating the protection device utilizes the step of forming the smaller apertures and forming their antifuse material layers simultaneously with forming the antifuse apertures.A static-charge protection device for an antifuse device includes an additional second-sized aperture larger in area than the first-sized antifuse apertures. Metal plug material is deposited and etched back. A layer of amorphous silicon antifuse material is formed and defined over the first and second sized apertures, the portion formed over the larger partially filled antifuse protection device cell being thinner.Type: GrantFiled: July 7, 1993Date of Patent: November 29, 1994Assignee: Actel CorporationInventors: Yeouchung Yen, Wenn-Jei Chen, Steve S. Chiang, Abdul R. Forouhi
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Patent number: 5367208Abstract: A user-programmable interconnect architecture, which may be used for logic arrays for digital and analog system design, is disclosed. In one embodiment, a plurality of logic cells or modules in a matrix are connected by vertical and horizontal wiring channels. The wiring channels may in turn be programmed by the user to interconnect the various logic cells to implement the required logic function. The wiring channels comprise wiring segments connected by normally open programmable. Elements situated at the intersection of any two segments to be connected.Type: GrantFiled: January 13, 1993Date of Patent: November 22, 1994Assignee: Actel CorporationInventors: Abbas El Gamal, Steve S. S. Chiang
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Patent number: 5316971Abstract: A method for programming antifuses having at least one metal electrode includes the steps of providing an antifuse programming voltage source, capable of supplying alternating positive and negative programming voltage pulses; providing a programming path from the antifuse programming voltage source to the antifuse; and providing a selected number of alternating positive and negative programming voltage pulses to the antifuse through the programming path.Type: GrantFiled: September 18, 1992Date of Patent: May 31, 1994Assignee: Actel CorporationInventors: Steve S. Chiang, Wenn-Jei Chen, Esam Elashmawi
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Patent number: D401919Type: GrantFiled: October 8, 1997Date of Patent: December 1, 1998Assignee: Sysgration Ltd.Inventor: M. S. Chiang