Abstract: An electrostatic discharge protection circuit is provided having a first electrically conductive element (such as a current sinking transistor) to couple between a power source and a first node. The first electrically conductive element has a control input terminal. A discharge path control circuit having an output terminal couples to the control input terminal of the first electrically conductive element. A timer circuit having an output terminal couples to the input terminal of the discharge path control circuit. A ring oscillator timer circuit having an output terminal couples to an input terminal of the timer circuit. The ring oscillator timer circuit may include a series of inverter circuits and/or counter circuits (such as flip-flop circuits).

Abstract: Apparatus and systems, as well as methods and articles, may operate to transmit an initial pulse to a directional coupler, where the initial pulse has an initial amplitude and a timed overshoot of a selected duration. Further activities may include stepping down the initial amplitude to an amplitude approximately equal to the initial amplitude times a mode reflection coefficient squared. A tuning stub may be coupled to a charge line to transmit the initial pulse, and decoupled from the charge line to refrain from receiving an echo pulse associated with the initial pulse.

Abstract: A multi-stack power supply clamp circuit for providing electrostatic discharge (ESD) protection to enhance performance of advanced submicron processes is provided. The clamp circuit includes a bias voltage generator with low leakage and high current drive capabilities, and means to lighten current load on the voltage generator through reduced gate leakage. The bias voltage generator has includes a differential amplifier. The multi-stack clamp circuit provides voltage-tolerant ESD protection with optimized leakage, reduced sensitivity to operating conditions, and tolerance of increased gate current in new process technologies.

Abstract: Iron based amorphous steel alloy having a high Manganese content and being non-ferromagnetic at ambient temperature. The bulk-solidifying ferrous-based amorphous alloys are multicomponent systems that contain about 50 atomic percent iron as the major component. The remaining composition combines suitable mixtures of metalloids (Group b elements) and other elements selected mainly from manganese, chromium, and refractory metals. Various classes of non-ferromagnetic ferrous-based bulk amorphous metal alloys are obtained. One class is a high-manganese class that contains manganese and boron as the principal alloying components. Another class is a high manganese-high molybdenum class that contains manganese, molybdenum, and carbon as the principal alloying components. These bulk-solidifying amorphous alloys can be obtained in various forms and shape for various applications and utlizations. The good processability of these alloys can be attributed to the high reduced glass temperature Trg (e.g., about 0.6 to 0.

Abstract: The present invention relates to novel non-ferromagnetic amorphous steel alloys represented by the general formula: Fe—Mn-(Q)-B-M, wherein Q represents one or more elements selected from the group consisting of Sc, Y, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb and Lu, and M represents one or more elements selected from the group consisting of Cr, Co, Mo, C and Si. Typically the atomic percentage of the Q constituent is 10 or less. An aspect is to utilize these amorphous steels as coatings, rather than strictly bulk structural applications. In this fashion any structural metal alloy can be coated by various technologies by these alloys for protection from the environment. The resultant structures can utilize surface and bulk properties of the amorphous alloy.

Abstract: The present invention relates to novel non-ferromagnetic amorphous steel alloys represented by the general formula: Fe—Mn-(Q)-B-M, wherein Q represents one or more elements selected from the group consisting of Sc, Y, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb and Lu, and M represents one or more elements selected from the group consisting of Cr, Co, Mo, C and Si. Typically the atomic percentage of the Q constituent is 10 or less. FIG. 2B represents a differential thermal analysis plot for several exemplary alloys according to the invention.

Abstract: An electrostatic discharge circuit may include an RC timer that may be used to control the operation of two or more tiers within the ESD circuit.

Abstract: A reduced capacitance diode. A first conductive layer provides conductive interconnects for pad and supply diffusion regions in a diode. A second conductive layer includes a first portion to couple the pad diffusion regions to a pad and a second portion to couple the supply diffusion regions to a voltage supply. Lines of the first and second conductive layers are substantially parallel to each other in a diode region of the diode. Further, for one aspect, a tap for the diode to be coupled to a supply is wider than a minimum width.

Abstract: An electrostatic discharge protection circuit is provided having a first electrically conductive element (such as a current sinking transistor) to couple between a power source and a first node. The first electrically conductive element has a control input terminal. A discharge path control circuit having an output terminal couples to the control input terminal of the first electrically conductive element. A timer circuit having an output terminal couples to the input terminal of the discharge path control circuit. A ring oscillator timer circuit having an output terminal couples to an input terminal of the timer circuit. The ring oscillator timer circuit may include a series of inverter circuits and/or counter circuits (such as flip-flop circuits).

Abstract: A portable speech signal preprocessing (SSP) device having a microphone for receiving spoken speech and background noise, a digital signal processor (DSP) for processing the received noise into feature vectors, a coupler for coupling to a communication device and for transmission over a communication channel. An automatic speech/speaker recognition (ASSR) server receives over the communication channel the preprocessed speech data and recognizes the spoken speech/speaker. A system having the portable SSP device and the ASSR server can be used to remotely activate, reset, or change PIN codes in smartcards, magnetic cards, or electronic money cards.

Abstract: Briefly, in accordance with one embodiment of the invention, an electrostatic discharge circuit may include an RC timer that may be used to control the operation of two or more tiers within the ESD circuit.

Abstract: This invention is directed to a continuously cleanable, high performance filtration apparatus and a method for using the apparatus. The apparatus is a radial inflow centrifugal filtration device, which includes a filter element located within a chamber and rotatably coupled to a filtered fluid outlet in a bulkhead that abuts the chamber. The filter element is generally tubular, its side-walls encircling and, thus, defining an interior plenum. The filter element side-walls incorporate a filter media, preferably a laminated microporous membrane filter media. The filter element is rotatably coupled at the filtered fluid outlet by a seal which can maintain a seal as filter element rotates. Additionally, the device can include a boundary layer momentum transfer device made up of a plurality of stacked annular disks having central openings, each disk separated from adjacent disks by a desired gap. The central openings define a cavity in which the filter element is mounted.

Abstract: A portable acoustic signal (speech signal) preprocessing (SSP) device for accessing an automatic speech/speaker recognition (ASSR) server comprises a microphone for converting sound including speech, silence and background noise signals to analog signals; an analog signals to digital converter for converting the analog signals to digital signals; a digital signal processor (DSP) for generating feature vector data representing the digitized speech and silence/background noise, and for generating channel characterization signals; and an acoustic coupler for converting the feature vector data and the characterization signals to acoustic signals and coupling the acoustic signals to a communication channel to access the ASSR server to perform speech and speaker recognition at a remote location. The SSP device may also be configured to compress and encrypt data transmitted to the ASSR server via the DSP and encryption keys stored in a memory.

Abstract: A process for the fabrication of an MOSFET device includes the formation of a buffer layer (28) overlying the surface of a semiconductor substrate (14) adjacent to a gate electrode (18). A defect compensating species is diffused through the buffer layer (28) and through a gate dielectric layer (12) to form a defect-compensating region (30) at the surface (14) of the semiconductor substrate (10). The defect-compensating region (30) in conjunction with the buffer layer (28) minimize and control the population of point defects in the channel region (22) of the semiconductor substrate (10). By controlling the population of point defects in the channel region (22), a substantially uniform doping profile is maintained in a shallow doped region (16) formed in the semiconductor substrate (10) at the substrate surface (14). The maintenance of a uniform doping profile in the shallow doped region (16) results in improved threshold voltage stability as the lateral dimension of the channel region (22) is reduced.

Abstract: The reliability of integrated circuits fabricated with trench isolation is improved by increasing the thickness of the gate dielectric overlying the trench corner. After the trench isolation region (40, 56) has been formed a thin layer of silicon dioxide (44) is chemically vapor deposited over the trench isolation region (44) and the adjacent active region (23). A transistor gate electrode (46) is subsequently formed over the thin layer of silicon dioxide (44). The thin layer of silicon dioxide (44) increases the thickness of the gate dielectric that lies between the transistor gate electrode (46) and the trench corner, and therefore the breakdown voltage of the gate dielectric at the trench corner is increased.

Abstract: The reliability of integrated circuits fabricated with trench isolation is improved by increasing the thickness of the gate dielectric overlying the trench corner. After the trench isolation region (40, 56) has been formed a thin layer of silicon dioxide (44) is chemically vapor deposited over the trench isolation region (44) and the adjacent active region (23). A transistor gate electrode (46) is subsequently formed over the thin layer of silicon dioxide (44). The thin layer of silicon dioxide (44) increases the thickness of the gate dielectric that lies between the transistor gate electrode (46) and the trench corner, and therefore the breakdown voltage of the gate dielectric at the trench corner is increased.

Abstract: A planar surface (24) is obtained in a semiconductor device (10) having regions of differing material composition by means of a non-selective planarization process. The non-selective planarization process removes insulating material and conductive material at substantially the same rate. In one embodiment of the invention, stud vias (22) are formed by the removal of portions of a conductive layer (20) overlying the surface of an interlevel dielectric layer (16). Once the conductive layer (20) has been removed, the planarization process is continued and surface portions of the interlevel dielectric layer (16) are also removed. Upon completion of the process a planar surface (24) is formed having regions of conductive material and insulating material.

Abstract: A non-silyated, ternary boron nitride film (18, 38) is provided for semiconductor device applications. The non-silyated, ternary boron nitride film is preferably formed by plasma-enhanced chemical vapor deposition using non-silyated compounds of boron, nitrogen, and either oxygen, germanium, germanium oxide, fluorine, or carbon. In one embodiment, boron oxynitride (BNO) is deposited in a plasma-enhanced chemical vapor deposition reactor using ammonia (NH.sub.3), diborane (B.sub.2 H.sub.6), and nitrous oxide (N.sub.2 O). The BNO film has a dielectric constant of about 3.3 and exhibits a negligible removal rate in a commercial polishing apparatus. Because of its low dielectric constant and high hardness, the ternary boron nitride film formed in accordance with the invention can be advantageously used as a polish-stop layer and as a interlevel dielectric layer in a semiconductor device.

Abstract: A trench structure (10) using germanium silicate. The trench structure (10) has a substrate material (12) and a hard mask material (14) that overlies the substrate material (12). An opening is formed in the hard mask material and the opening is used to form a trench (16) in the substrate material (12). The trench (16) has a sidewall portion and a bottom portion. A barrier (18 and 20) is formed overlying the bottom portion of the trench (16) and adjacent to the sidewall portion of the trench (16). A planar germanium silicate region (22) is formed overlying the barrier (18 and 20).

Abstract: A trench structure (10) using germanium silicate. The trench structure (10) has a substrate material (12) and a hard mask material (14) that overlies the substrate material (12). An opening is formed in the hard mask material and the opening is used to form a trench (16) in the substrate material (12). The trench (16) has a sidewall portion and a bottom portion. A barrier (18 and 20) is formed overlying the bottom portion of the trench (16) and adjacent to the sidewall portion of the trench (16). A planar germanium silicate region (22) is formed overlying the barrier (18 and 20).