Patents by Inventor S. Sims

S. Sims has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140113457
    Abstract: The embodiments herein focus on plasma enhanced atomic layer deposition (PEALD) processes using pulsed plasmas. While conventional PEALD processes use continuous wave plasmas during the plasma exposure/conversion operation, the embodiments herein utilize a pulsed plasma during this operation to achieve a film with high quality sidewalls. Because conventional PEALD techniques result in films having high quality at the bottom and top of a feature, but low quality on the sidewalls, this increased sidewall quality in the disclosed methods corresponds to a film that is overall more uniform in quality compared to that achieved with conventional continuous wave plasma techniques.
    Type: Application
    Filed: December 30, 2013
    Publication date: April 24, 2014
    Inventors: James S. Sims, Jon Henri, Kathryn M. Kelchner, Sathish Babu S. V. Janjam, Shane Tang
  • Publication number: 20130334344
    Abstract: Semiconductor processing chamber showerheads with contoured faceplates, as well as techniques for producing such faceplates, are provided. Data describing deposition rate as a function of gap distance between a reference showerhead faceplate and a reference substrate may be obtained, as well as data describing deposition rate as a function of location on the substrate when the reference showerhead and the reference substrate are in a fixed arrangement with respect to each other. The two data sets may be used to determine offsets from a reference plane associated with the faceplate that determine a contour profile to be used with the faceplate.
    Type: Application
    Filed: July 3, 2012
    Publication date: December 19, 2013
    Inventors: Karl F. Leeser, James S. Sims
  • Patent number: 8512818
    Abstract: A highly tensile dielectric layer is generated on a heat sensitive substrate while not exceeding thermal budget constraints. Cascaded ultraviolet (UV) irradiation is used to produce highly tensile films to be used, for example, in strained NMOS transistor architectures. Successive UV radiation of equal or shorter wavelengths with variable intensity and duration selectively breaks bonds in the Si—N matrix and minimizes shrinkage and film relaxation. Higher tensile stress than a non-cascaded approach may be obtained.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: August 20, 2013
    Assignee: Novellus Systems, Inc.
    Inventors: Bhadri Varadarajan, Gengwei Jiang, Sirish K. Reddy, James S. Sims
  • Patent number: 8362571
    Abstract: Transistor architectures and fabrication processes generate channel strain without adversely impacting the efficiency of the transistor fabrication process while preserving the material quality and enhancing the performance of the resulting transistor. Transistor strain is generated is PMOS devices using a highly compressive post-salicide amorphous carbon capping layer applied as a blanket over on at least the source and drain regions. The stress from this capping layer is uniaxially transferred to the PMOS channel through the source-drain regions to create compressive strain in PMOS channel.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: January 29, 2013
    Assignee: Novellus Systems, Inc.
    Inventors: Qingguo Wu, James S. Sims, Mandyam Sriram, Seshasayee Varadarajan, Haiying Fu, Pramod Subramonium, Jon Henri, Sirish Reddy
  • Publication number: 20120240318
    Abstract: A hinge for attaching a toilet seat to irregularly spaced toilet bowl mounting holes, the hinge body having a mounting plate cooperating with a bowl mounting hole and having a plurality of interconnected fixing holes for receiving a fixing bolt in one of a plurality of selected positions. An integral flexibly hinged cover closes over the hinge body and is frictionally secured thereto for concealing the fixing holes and bolt, and giving the hinge a finished appearance.
    Type: Application
    Filed: March 22, 2011
    Publication date: September 27, 2012
    Applicant: Jones Stephens Corporation
    Inventor: Edward S. Sims
  • Patent number: 8211510
    Abstract: A highly tensile dielectric layer is generated on a heat sensitive substrate while not exceeding thermal budget constraints. Cascaded ultraviolet (UV) irradiation is used to produce highly tensile films to be used, for example, in strained NMOS transistor architectures. Successive UV radiation of equal or shorter wavelengths with variable intensity and duration selectively breaks bonds in the Si—N matrix and minimizes shrinkage and film relaxation. Higher tensile stress than a non-cascaded approach may be obtained.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: July 3, 2012
    Assignee: Novellus Systems, Inc.
    Inventors: Bhadri Varadarajan, Gengwei Jiang, Sirish K. Reddy, James S. Sims
  • Patent number: 7998881
    Abstract: Transistor architectures and fabrication processes generate channel strain without adversely impacting the efficiency of the transistor fabrication process while preserving the material quality and enhancing the performance of the resulting transistor. Transistor strain is generated is PMOS devices using a highly compressive post-salicide boron doped carbon capping layer applied as a blanket over on at least the source and drain regions. The stress from this capping layer is uniaxially transferred to the PMOS channel through the source-drain regions to create compressive strain in PMOS channel.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: August 16, 2011
    Assignee: Novellus Systems, Inc.
    Inventors: Qingguo Wu, James S. Sims, Mandyam Sriram, Seshasayee Varadarajan, Akhil Singhal
  • Patent number: 7906817
    Abstract: Transistor architectures and fabrication processes generate channel strain without adversely impacting the efficiency of the transistor fabrication process while preserving the material quality and enhancing the performance of the resulting transistor. Transistor strain is generated is PMOS devices using a highly compressive post-salicide amorphous carbon capping layer applied as a blanket over on at least the source and drain regions. The stress from this capping layer is uniaxially transferred to the PMOS channel through the source-drain regions to create compressive strain in PMOS channel.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: March 15, 2011
    Assignee: Novellus Systems, Inc.
    Inventors: Qingguo Wu, James S. Sims, Mandyam Sriram, Seshasayee Varadarajan, Haiying Fu, Pramod Subramonium, Jon Henri, Sirish Reddy
  • Patent number: 7854942
    Abstract: Compositions, food products or beverages for ameliorating the symptoms of celiac disease or gluten sensitive enteropathy comprising egg yolk antibodies against gluten, including gliadin, high molecular glutenin, low molecular glutenin and mixtures of the peptides. The antibodies may be produced by immunizing egg laying fowl with immunogenic preparations of gluten and harvesting the eggs and egg yolks.
    Type: Grant
    Filed: April 18, 2005
    Date of Patent: December 21, 2010
    Assignee: The Governors of the University of Alberta
    Inventors: Hoon Sunwoo, Jeong S. Sim
  • Patent number: 7745346
    Abstract: A method for forming a silicon-based dielectric film on a substrate with a single deposition process operation using pulsed plasma enhanced chemical vapor deposition (PECVD) wherein the high frequency radio frequency power of the plasma is pulsed, allows enhanced control, efficiency and product quality of the PECVD process. Pulsing the high frequency RF power of the plasma reduces the deposited film thickness per unit time the high frequency RF power of the plasma is on. This yields silicon-based dielectric films that are both thin and conformal.
    Type: Grant
    Filed: October 17, 2008
    Date of Patent: June 29, 2010
    Assignee: Novellus Systems, Inc.
    Inventors: Dennis Hausmann, James S. Sims, Andrew Antonelli, Sesha Varadarajan, Bart Van Schravendijk
  • Publication number: 20100099271
    Abstract: A method for forming a silicon-based dielectric film on a substrate with a single deposition process operation using pulsed plasma enhanced chemical vapor deposition (PECVD) wherein the high frequency radio frequency power of the plasma is pulsed, allows enhanced control, efficiency and product quality of the PECVD process. Pulsing the high frequency RF power of the plasma reduces the deposited film thickness per unit time the high frequency RF power of the plasma is on. This yields silicon-based dielectric films that are both thin and conformal.
    Type: Application
    Filed: October 17, 2008
    Publication date: April 22, 2010
    Applicant: NOVELLUS SYSTEMS, INC.
    Inventors: Dennis Hausmann, James S. Sims, Andrew Antonelli, Sesha Varadarajan, Bart Van Schravendijk
  • Publication number: 20080281445
    Abstract: This device is built on many features. It relates to an Mp3-player which gives it the capability to be used with your car stereo system. In short, you will have the ability to use your Mp3-player with the use of your car stereo. You will also have the ability to install and use this invention without the need for attachments such as USB cords. This device will also enable you to download music from your PC or directly from your car stereo. You will be able to play DVD's as well as CD's that have been ripped or burned from your PC or car Stereo. It will include broadband radio (AM&FM) DVD player, high speed copier, bass and treble tuner, clock and timer.
    Type: Application
    Filed: May 7, 2007
    Publication date: November 13, 2008
    Inventor: Lewis S. Sims Angel
  • Patent number: 7327001
    Abstract: A salicide layer is deposited on the source/drain regions of a PMOS transistor. A dielectric capping layer having residual compressive stress is formed on the salicide layer by depositing a plurality of PECVD dielectric sublayers and plasma-treating each sublayer. Compressive stress from the dielectric capping layer is uniaxially transferred to the PMOS channel through the source-drain regions to create compressive strain in the PMOS channel. To form a compressive dielectric layer, a deposition reactant mixture containing A1 atoms and A2 atoms is provided in a vacuum chamber. Element A2 is more electronegative than element A1, and A1 atoms have a positive oxidation state and A2 atoms have a negative oxidation state when A1 atoms are bonded with A2 atoms. A deposition plasma is generated by applying HF and LF radio-frequency power to the deposition reactant mixture, and a sublayer of compressive dielectric material is deposited.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: February 5, 2008
    Assignee: Novellus Systems, Inc.
    Inventors: Akhil Singhal, James S. Sims, Bhadri N. Varadarajan
  • Patent number: 7214630
    Abstract: A salicide layer is deposited on the source/drain regions of a PMOS transistor. A dielectric capping layer having residual compressive stress is formed on the salicide layer by depositing a plurality of PECVD dielectric sublayers and plasma-treating each sublayer. Compressive stress from the dielectric capping layer is uniaxially transferred to the PMOS channel through the source-drain regions to create compressive strain in the PMOS channel. To form a compressive dielectric layer, a deposition reactant mixture containing A1 atoms and A2 atoms is provided in a vacuum chamber. Element A2 is more electronegative than element A1, and A1 atoms have a positive oxidation state and A2 atoms have a negative oxidation state when A1 atoms are bonded with A2 atoms. A deposition plasma is generated by applying HF and LF radio-frequency power to the deposition reactant mixture, and a sublayer of compressive dielectric material is deposited.
    Type: Grant
    Filed: May 6, 2005
    Date of Patent: May 8, 2007
    Assignee: Novellus Systems, Inc.
    Inventors: Bhadri N. Varadarajan, James S. Sims, Akhil Singhal
  • Patent number: 7041543
    Abstract: Transistor architectures and fabrication processes generate channel strain without adversely impacting the efficiency of the transistor fabrication process while preserving the material quality and enhancing the performance of the resulting transistor. Transistor strain is generated is NMOS devices using a highly tensile post-salicide silicon nitride capping layer on the source and drain regions. The stress from this capping layer is uniaxially transferred to the NMOS channel through the source-drain regions to create tensile strain in NMOS channel.
    Type: Grant
    Filed: August 20, 2004
    Date of Patent: May 9, 2006
    Assignee: Novellus Systems, Inc.
    Inventors: Bhadri Varadarajan, William W. Crew, James S. Sims
  • Publication number: 20050087649
    Abstract: Applicants' ATR system is weather-agile because it is comprised of a primary target sensing means that is capable of surveilling the target scene in foul or fair weather, and a secondary target sensing means that is also capable of sensing targets in various weather. The primary and secondary sensing means communicate through a control center so that ultimately, among several weapons available, the most strategically located and equipped weapon is activated for the destruction of a selected target, given the weather. The control center accomplishes the communication by receiving the sensed target signature from the primary sensing means, processing the signature using database already resident in the center and transmitting the processed target signature to the weapon possessing the greatest potential for successfully destroying the target.
    Type: Application
    Filed: September 29, 2003
    Publication date: April 28, 2005
    Inventors: S. Sims, William Pittman
  • Patent number: 6533298
    Abstract: A carrying device for transporting items over hard surfaces and soft surfaces including a carrier body having a top surface and a bottom surface, the carrier body having a recessed portion in the top surface thereof, the recessed portion having a plurality of tabs extending inwardly therefrom, a storage container adapted for placement in the recessed portion, the storage container having elongated slots therein for receipt of the tabs in the elongated slots to secure the containers to the carrier body, and at least two wheels connected to the carrier body for rolling the carrier body over hard surfaces.
    Type: Grant
    Filed: March 12, 2001
    Date of Patent: March 18, 2003
    Inventor: Charles S. Sims
  • Publication number: 20020125668
    Abstract: A carrying device for transporting items over hard surfaces and soft surfaces including a carrier body having a top surface and a bottom surface, the carrier body having a recessed portion in the top surface thereof, the recessed portion having a plurality of tabs extending inwardly therefrom, a storage container adapted for placement in the recessed portion, the storage container having elongated slots therein for receipt of the tabs in the elongated slots to secure the containers to the carrier body, and at least two wheels connected to the carrier body for rolling the carrier body over hard surfaces.
    Type: Application
    Filed: March 12, 2001
    Publication date: September 12, 2002
    Inventor: Charles S. Sims
  • Patent number: 6099867
    Abstract: A nutraceutical composition comprising water insoluble antler powder or water soluble antler powder or a combination of both. Also disclosed is a method of producing antler powder, either water soluble, water insoluble or a combination of both.
    Type: Grant
    Filed: June 26, 1998
    Date of Patent: August 8, 2000
    Inventor: Jeong S. Sim
  • Patent number: 5638324
    Abstract: The present invention relates to a flash memory device and pre-program only the memory cells which keep the erase state by verifying whether the memory cells are programmed before performing the pre-program operation to prevent the memory cell from being over-programmed at the time of pre-program. Accordingly, there are excellent effects in that the reliability of the device can be improved by preventing the memory cell from being over-programmed and the operation speed of the device can be improved by reducing the time required in the pre-program operation.
    Type: Grant
    Filed: December 21, 1995
    Date of Patent: June 10, 1997
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: Hyun S. Sim