Abstract: A computing system for implementing at least one electronic circuit with gain comprises at least one two-dimensional molecular switch array. The molecular switch array is formed by assembling two or more crossed planes of wires into a configuration of devices. Each device comprises a junction formed by a pair of crossed wires and at least one connector species that connects the pair of crossed wires in the junction. The junction has a functional dimension in nanometers, and includes a switching capability provided by both (1) one or more connector species and the pair of crossed wires and (2) a configurable nano-scale wire transistor having a first state that functions as a transistor and a second state that functions as a conducting semiconductor wire. Specific connections are made to interconnect the devices and connect the devices to two structures that provide high and low voltages.

Abstract: Embodiments of the present invention are employ dynamical, nanoscale devices, including memristive connections between nanowires, for constructing parallel, distributed, dynamical computational networks and systems, including perceptron networks and neural networks. In many embodiments of the present invention, neuron-like computational devices are constructed from silicon-based microscale and/or submicroscale components, and interconnected with one another by dynamical interconnections comprising nanowires and memristive connections between nanowires. In many massively parallel, distributed, dynamical computing systems, including the human brain, there may be a far greater number of interconnections than neuron-like computational nodes. Use of dynamical nanoscale devices for these connections results in enormous design, space, energy, and computational efficiencies.

Abstract: The present invention is directed toward a system for forming miter joints including a miter saw and an angle gauge. The miter saw includes a platform with a kerf slot and a pair of arcuate slots. Each arcuate slot includes an associated rail located on the underside of the platform. A fence is coupled to each of the rails such that the fence may be pivoted with respect to the platform. The angle measurement tool is a one-handed tool including spring loaded paddles that measure the angle between intersecting surfaces. The angle measurement tool connects to the miter saw to permit the transfer of the measured angle to the fences.

Abstract: Embodiments of the present invention are directed to mixed-scale electronic interfaces, included in integrated circuits and other electronic devices, that provide for dense electrical interconnection between microscale features of a predominantly microscale or submicroscale layer and nanoscale features of a predominantly nanoscale layer. A method is provided for fabricating a nanoscale/microscale interface having a microscale layer and a predominantly nanoscale layer.

Abstract: Embodiments of the present invention include hybrid microscale-nanoscale neuromorphic integrated circuits that include an array of analog computational cells fabricated on an integrated-circuit-substrate. The analog electronic circuitry within each computational cell connected to one or more pins of a first type and to one or more pins of a second type that extend approximately vertically from the computational cells. The computational cells are additionally interconnected by one or more nanowire-interconnect layers, each nanowire-interconnect layer including two nanowire sublayers on either side of a memristive sublayer, with each nanowire in each nanowire sublayer of an interconnect layer connected to a single computational-cell pin and to a number of nanowires in the other nanowire sublayer of the interconnect layer.

Abstract: Various embodiments of the present invention are directed to three-dimensional crossbar arrays. In one aspect of the present invention, a three-dimensional crossbar array includes a plurality of crossbar arrays, a first demultiplexer, a second demultiplexer, and a third demultiplexer. Each crossbar array includes a first layer of nanowires, a second layer of nanowires overlaying the first layer of nanowires, and a third layer of nanowires overlaying the second layer of nanowires. The first demultiplexer is configured to address nanowires in the first layer of nanowires of each crossbar array, the second demultiplexer is configured to address nanowires in the second layer of nanowires of each crossbar array, and the third demultiplexer is configured to supply a signal to the nanowires in the third layer of nanowires of each crossbar array.

Abstract: A chlorinated rubber composition which is resistant to various fluids such as transmission fluids comprises a blend of a chlorinated polyethylene elastomer, an ethylene acrylic elastomer and/or polyacrylic rubbers, and optionally a chlorosulfonated polyethylene. The rubber composition has many uses such as a tube and generally contains various additives such as fillers, plasticizers, vulcanizing agents, and the like. A heat resistant rubber composition comprises a blend of a chlorinated polyethylene elastomer, an ethylene-acrylic elastomer and/or polyacrylic rubbers, an ethylene-octene copolymer, and an ethylene-propylene-diene terpolymer, and the same can be used as a cover or jacket as on the above chlorinated rubber tube.

Abstract: Various embodiments of the present invention are directed to photonic-interconnection-based compute clusters that provide high-speed, high-bandwidth interconnections between compute cluster nodes. In one embodiment of the present invention, the compute cluster includes a photonic interconnection having one or more optical transmission paths for transmitting independent frequency channels within an optical signal to each node in a set of nodes. The compute cluster includes one or more photonic-interconnection-based writers, each writer associated with a particular node, and each writer encoding information generated by the node into one of the independent frequency channels. A switch fabric directs the information encoded in the independent frequency channels to one or more nodes in the compute cluster.

Abstract: Embodiments of the present invention are directed to mixed-scale electronic interfaces, included in integrated circuits and other electronic devices, that provide for dense electrical interconnection between microscale features of a predominantly microscale or submicroscale layer and nanoscale features of a predominantly nanoscale layer. The predominantly nanoscale layer, in one embodiment of the present invention, comprises a tessellated pattern of submicroscale or microscale pads densely interconnected by nanowire junctions between sets of parallel, closely spaced nanowire bundles. The predominantly submicroscale or microscale layer includes pins positioned complementarily to the submicroscale or microscale pads in the predominantly nanoscale layer. Pins can be configured according to any periodic tiling of the microscale layer.

Abstract: Embodiments of the present invention are directed to mixed-scale electronic interfaces, included in integrated circuits and other electronic devices, that provide for dense electrical interconnection between microscale features of a predominantly microscale or submicroscale layer and nanoscale features of a predominantly nanoscale layer. A method is provided for fabricating a nanoscale/microscale interface having a microscale layer and a predominantly nanoscale layer.

Abstract: Methods for inputting a data-value pattern into a nanowire crossbar, for inputting a data-value pattern into a nanowire crossbar that support computer instructions stored in a computer-readable medium, and for distributing a received data value to each of a set of nanowires that support control logic implemented in logic circuits are provided. First and second nanoscale shift registers are employed, the first having output signal lines that form or interconnect with a first parallel set of nanowire-crossbar nanowires and the second having output signal lines that form or interconnect with a second parallel set of nanowire-crossbar nanowires. A first pattern of values is stored in the first shift register and a second pattern of values is stored in the second shift register using voltage signals below the WRITE voltage for junctions of the crossbar. Voltage signals greater than or equal to the WRITE threshold are applied for junctions of the crossbar to write the pattern of data values into the crossbar.

Abstract: Reconfigurable logic devices and methods of programming the devices are disclosed. The logic device includes a look-up table (LUT) and at least one storage element configured for sampling LUT output signals. The LUT comprises a plurality of input signals, an array of programmable impedance devices operably coupled to the input signals, and the LUT output signals. Each programmable impedance device in the array includes a first electrode operably coupled to one of the input signal, a second electrode disposed to form a junction wherein the second electrode at least partially overlaps the first electrode, and a programmable material disposed between the first electrode and the second electrode. The programmable material operably couples the first electrode and the second electrode such that each programmable impedance device exhibits a non-volatile programmable impedance. The array may be configured as a one-dimensional or two-dimensional array.

Abstract: The present invention is generally related to products and methods for leveling, plumbing, squaring and a frame to a structure during its attachment.

Abstract: Methods for inputting a data-value pattern into a nanowire crossbar, for inputting a data-value pattern into a nanowire crossbar that support computer instructions stored in a computer-readable medium, and for distributing a received data value to each of a set of nanowires that support control logic implemented in logic circuits are provided. First and second nanoscale shift registers are employed, the first having output signal lines that form or interconnect with a first parallel set of nanowire-crossbar nanowires and the second having output signal lines that form or interconnect with a second parallel set of nanowire-crossbar nanowires. A first pattern of values is stored in the first shift register and a second pattern of values is stored in the second shift register using voltage signals below the WRITE voltage for junctions of the crossbar. Voltage signals greater than or equal to the WRITE threshold are applied for junctions of the crossbar to write the pattern of data values into the crossbar.

Abstract: Various embodiments of the present invention are directed to nanowire crossbars that use configurable, tunneling resistor junctions to electronically implement logic gates. In one embodiment of the present invention, a method for implementing a logic gate comprises: providing a first layer of approximately parallel nanowires; interconnecting the first layer of approximately parallel nanowires with a second layer of approximately parallel nanowires through configurable, tunneling resistor junctions; selecting nanowires from among the first and second layer of nanowires to carry input and output electrical signals representing logical values; applying electrical signals representing input logical values to the input nanowires; and detecting an electrical signal representing an output logical value on the output nanowires.

Abstract: Embodiments of the present invention are directed to mixed-scale electronic interfaces, included in integrated circuits and other electronic devices, that provide for dense electrical interconnection between microscale features of a predominantly microscale or submicroscale layer and nanoscale features of a predominantly nanoscale layer. The predominantly nanoscale layer, in one embodiment of the present invention, comprises a tessellated pattern of submicroscale or microscale pads densely interconnected by nanowire junctions between sets of parallel, closely spaced nanowire bundles. The predominantly submicroscale or microscale layer includes pins positioned complementarily to the submicroscale or microscale pads in the predominantly nanoscale layer.

Abstract: Various embodiments of the present invention are directed to nanowire crossbars that use configurable, tunneling resistor junctions to electronically implement logic gates. In one embodiment of the present invention, a nanowire crossbar comprises two or more layers of approximately parallel nanowires, and a number of configurable, tunneling resistor junctions that each interconnects a nanowire in a first layer of approximately parallel nanowires with a nanowire in a second layer of approximately parallel nanowires.

Abstract: One embodiment of the present invention is a nanoscale shift register that can be used, in certain nanoscale and mixed-scale logic circuits, to distribute an input signal to individual nanowires of the logic circuit. In a described embodiment, the nanoscale shift register includes two series of nanoscale latches, each series controlled by common latch-control signals. Internal latches of each series of latches are alternatively interconnected with a previous latch of the other series and a next latch of the other series by two series of gates, each controlled by a gate signal line.

Abstract: One embodiment of the present invention is a method for fabricating a nanoscale shift register. In a described embodiment, a nanoimprinting-resist layer applied above a silicon-on-insulator substrate is nanoimprinted to form troughs and trough segments. The silicon layer exposed at the bottom of the troughs and trough segments is then etched, and a conductive material is deposited into the troughs to form nanowires and into the trough segments to form nanowire segments. The exposed surfaces of nanowires are coated with a protective coating, and the conductive material of the nanowire segments is then removed to produce trough segments etched through the nanoimprinting resist and the silicon layer.