Abstract: Embodiments of the present invention implement computing circuits comprising a number of interconnectable nanoscale computational stages. Each nanoscale computational stage includes: (1) a nanoscale logic array; and (2) a number of nanoscale latch arrays interconnected with the configurable logic array. Each nanoscale computational stage receives signals and passes the signals through the nanoscale logic array and to a nanoscale latch array. Signals output from the nanoscale latch array can be routed to another nanoscale computational stage or out of the computing circuit.

Abstract: Embodiments of the present invention are related to nanoscale multiplexers and demultiplexers that employ randomly fabricated interconnections between nanowire signal lines and microscale or sub-microscale address lines. A greater number of address lines than a minimal number of address lines needed for unique addressing in a deterministic, non-randomly fabricated multiplexer or demultiplexer are used. The number of address lines in excess of the minimal number of address lines needed for unique addressing in a deterministic multiplexer or demultiplexer are referred to as supplemental address lines.

Abstract: Various embodiments of the present invention are directed to a signal-storing nanowire-crossbar latch array. In one embodiment, the signal-storing nanowire-crossbar latch array is fabricated from three signal lines, including an enable line and two control lines, that cross and intersect with a number of signal wires. Signals are stored in the nanowire-crossbar latch array, and output from the nanowire-crossbar latch array, by applying an input signal to each signal wire and applying selected voltages and voltage pulses to the control lines. In alternate embodiments, a second enable line that crosses and interconnects with each signal wire is added to the nanowire-crossbar latch array.

Abstract: Various embodiments of the present invention provide methods for allocating nanowire junctions in a nanowire crossbar having one or more randomly distributed non-functional crossbar nanowire junctions. In certain embodiments, the method constructs a circuit graph based on the circuit and constructs a crossbar graph based on the nanowire crossbar. A search is then conducted, in the embodiments, in order to determine a monomorphism that respectively maps the nodes and edges of the circuit graph to a subset of nodes and a subset of edges of the crossbar graph. The subset of nodes and subset of edges of the crossbar graph can then be used to allocate nanowire junctions in the nanowire crossbar.

Abstract: A circuit arrangement and method for interfacing a node and a data fabric. In a computing arrangement that includes a plurality of nodes intercoupled by the data fabric, each node is assigned to one of a plurality of partitions. A node-interface circuit is configured to interface with the source node, and a translation circuit translates data between a first format compatible with the nodes and a second format compatible with the data fabric. An access control circuit either enables or disables transmission of data from the source node based on whether the source and destination nodes are in the same partition.

Abstract: Various embodiments of the present invention are directed to implementation and use of logic-state-storing, impedance-encoded nanoscale, impedance-encoded latches that store logic values as impedance states within nanoscale electronic circuits that employ impedance-driven logic. In certain of these embodiments, use of nanoscale, impedance-encoded latches together with nanoscale electronic circuits that employ impedance-driven logic avoids cumulative degradation of voltage margins along a cascaded series of logic circuits and provides for temporary storage of intermediate logic values, allowing for practical interconnection of nanowire-crossbar-implemented logic circuits through nanoscale, impedance-encoded latches to other nanowire-crossbar-implemented logic circuits in order to implement complex, nanoscale-logic-circuit pipelines, nanoscale-logic-circuit-based state machines, and other complex logic devices with various different interconnection topologies and corresponding functionalities.

Abstract: An impeller assembly includes a molded impeller and an insert within the impeller. The insert includes an unthreaded sleeve and a shoulder adjacent the sleeve for locating the impeller and the insert during manufacturing and installation. Methods of manufacturing and installing are also disclosed.

Abstract: Various embodiments of the present invention provide methods for designing multilayer nanowire crossbars that are functionally equivalent to two-layer nanowire-crossbar designs. Given a two-layer nanowire-crossbar design having two or more columns of microregions, in certain embodiments, the method conceptually folds the two-layer nanowire crossbar between columns of microregions. The folded nanowires, located in the conceptually folded, two-layer nanowire-crossbar design, are collapsed into shorter length nanowires to give a multilayer nanowire-crossbar design that includes the same number of nanowire junctions as in the two-layer nanowire-crossbar design.

Abstract: One embodiment of the present invention is an array of nanoscale latches interconnected by a nanowire bus to form a latch array. Each nanoscale latch in the nanoscale-latch array serves as a nanoscale register, and is driven by a nanoscale control line. Primitive operations for the latch array can be defined as sequences of one or more inputs to one or more of the nanowire data bus and nanoscale control lines. In various latch-array embodiments of the present invention, information can be transferred from one nanoscale latch to another nanoscale latch in a controlled fashion, and sequences of information-transfer operations can be devised to implement arbitrary Boolean logic operations and operators, including NOT, AND, OR, XOR, NOR, NAND, and other such Boolean logic operators and operations, as well as input and output functions.

Abstract: A lock set installation apparatus has a pair of hole saw guides which locate a hole to receive door operating members of a lock set. Each hole saw guide has at least one rail member which oppose one another. A lock bolt hole mechanism is movable and coupled with the rails. The lock bolt hole mechanism centers the lock bolt hole onto the door. A locking mechanism locks the hole saw guides with respect to one another to enable cutting of the door.

Abstract: Method and apparatus for reducing a number of storage elements in a synthesized synchronous circuit. In one embodiment, the circuit is represented as a directed, partitioned graph. The graph is divided into a plurality of time-ordered timeslots that are bounded by storage elements. The strongly-connected components (SCCs) in the graph are first identified. For each middle SCC where there is slack between the middle SCC and a first SCC and slack between the middle SCC and a second SCC, a time-slot-relative direction is selected for moving the middle SCC. The direction is selected as a function of a number of storage elements required for moving the middle SCC toward the first SCC versus moving the middle SCC toward the second SCC. The middle SCC is then moved in the selected time-slot-relative direction.

Abstract: A work box to be combined with a work table has a base with at least one extending side wall enclosing a tool retaining area. An interruption is formed in the base to define a gap for receiving a support on the work table. The support mounts the base and, in turn, the work box onto the support and the work table.

Abstract: An embodiment of the invention includes, parsing a source code, performing a plurality of optimizations on the parsed code, generating a plurality of configuration instruction sets based on the optimized source code and automatically selecting one of the plurality of generated configuration instruction sets according to a user defined criteria, the selected configuration instruction set being used to configure hardware.

Abstract: The present invention provides a method and apparatus to significantly accelerate the searching process based on the Monte Carlo principle and the lattice model. Specifically, the energy status of a lattice-based protein conformation is evaluated by modeling the folding process through a pipelined digital circuit using a number of state machines. The pipelined digital circuit reduces the time required for the determination of the energy status of a particular conformation and, therefore, significantly accelerates the searching speed for the lowest energy status. The present invention also permits real-time tuning of problem parameters by the experimenter.

Abstract: In one embodiment, a content addressable memory (CAM), includes: a word line driver configured to provide a driving signal; a tag memory including M word lines traversing through the tag memory and intersecting with 2N bit lines, where M and N are each suitable integer values, where each word line and each bit line is a single molecular wire; a search enable circuitry coupled to the word line driver and configured to allow the driving signal to be driven onto a subset of the word lines in the tag memory; and a match detection circuit coupled to the tag memory and configured to detect current flow on the horizontal word lines.