Abstract: A power converter including an inductor, a first power switch, a second power switch, a third power switch, a fourth power switch, a sixth power switch, a first flying capacitor, a third flying capacitor, a seventh power switch, an eighth power switch, a ninth power switch, a tenth power switch, a twelfth power switch, a second flying capacitor, and a fourth flying capacitor.

Abstract: A power converter and methods with an input terminal, a capacitor, a first output terminal, a second output terminal, an output switch between the first output terminal and the second output terminal, and an inductor are presented. A first terminal of the inductor is connected to the first output terminal. An input switch is connected between the input terminal and a first terminal of the capacitor. A first capacitive charging switch is connected between the first terminal of the capacitor and the second output terminal. A second capacitive charging switch is connected between the second output terminal and a second terminal of the capacitor. A ground switch is connected between the second terminal of the capacitor and a reference potential. The power converter can convert electrical power into electrical power for powering an external device d or into electrical power for charging an external energy storage device.

Abstract: A power converter and methods with an input terminal, a capacitor, a first output terminal, a second output terminal, an output switch between the first output terminal and the second output terminal, and an inductor are presented. A first terminal of the inductor is connected to the first output terminal. An input switch is connected between the input terminal and a first terminal of the capacitor. A first capacitive charging switch is connected between the first terminal of the capacitor and the second output terminal. A second capacitive charging switch is connected between the second output terminal and a second terminal of the capacitor. A ground switch is connected between the second terminal of the capacitor and a reference potential. The power converter can convert electrical power into electrical power for powering an external device d or into electrical power for charging an external energy storage device.

Abstract: Methods and systems are disclosed for protecting a host device from one or more power surges transmitted from a sink device. When a sink device is detected as being connected to the host device, a limited level of power is provided to the sink device over a power transmission line and the sink device is authenticated. A normal level of power is provided to the sink device only if the authentication is successful, otherwise a reduced level of power is provided.

Abstract: A power converter and method using a flying capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, and a driver circuit are presented. The first transistor is coupled between an input terminal and a first terminal of the flying capacitor. The second transistor is coupled between the first terminal of the flying capacitor and an output terminal. The third transistor is coupled between the output terminal and a second terminal of the flying capacitor. The fourth transistor is coupled between the second terminal of the flying capacitor and a reference potential. The driver circuit is coupled between a high side power rail and a low side power rail. There is a regulation circuit to regulate a high side voltage of the high side power rail such that the regulated high side voltage is independent of an input voltage at the input terminal.

Abstract: A power converter and methods with an input terminal, a capacitor, a first output terminal, a second output terminal, an output switch between the first output terminal and the second output terminal, and an inductor are presented. A first terminal of the inductor is connected to the first output terminal. An input switch is connected between the input terminal and a first terminal of the capacitor. A first capacitive charging switch is connected between the first terminal of the capacitor and the second output terminal. A second capacitive charging switch is connected between the second output terminal and a second terminal of the capacitor. A ground switch is connected between the second terminal of the capacitor and a reference potential. The power converter can convert electrical power into electrical power for powering an external device d or into electrical power for charging an external energy storage device.

Abstract: A power converter and method using a flying capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, and a driver circuit are presented. The first transistor is coupled between an input terminal and a first terminal of the flying capacitor. The second transistor is coupled between the first terminal of the flying capacitor and an output terminal. The third transistor is coupled between the output terminal and a second terminal of the flying capacitor. The fourth transistor is coupled between the second terminal of the flying capacitor and a reference potential. The driver circuit is coupled between a high side power rail and a low side power rail. There is a regulation circuit to regulate a high side voltage of the high side power rail such that the regulated high side voltage is independent of an input voltage at the input terminal.

Abstract: Power converters, charge pumps and methods which are capable of regulating output voltage are presented. A power converter has a capacitive element, a first transistor, a second transistor, a third transistor, and a fourth transistor. The first transistor is coupled between an input terminal and a first terminal of the capacitve element. The second transistor is coupled between the first terminal of the capacitve element and an output terminal. The third transistor is coupled between the output terminal and a second terminal of the capacitive element. The fourth transistor is coupled between the second terminal of the capacitive element and a reference potential. The power converter has a control circuit to control, during a first time interval of a voltage regulation mode, one of the four transistors such that the one of the four transistors is operated as a controllable power source for regulating an output voltage.

Abstract: A wired connection, such as USB-C, for charging a sink from a source, has a configuration channel and a power transmission channel. The presence of data on the configuration channel is used to determine that a cable has been disconnected from the power source. This charging system contains a capacitive power converter and a controller for controlling the capacitive power converter. There is also a configuration channel detector, which is arranged to detect the status of the configuration channel and to provide this status to the controller, so that the system can determine that the source has been detached from the bus when no configuration channel data is present.

Abstract: A wired connection, such as USB-C, for charging a sink from a source, has a configuration channel and a power transmission channel. The presence of data on the configuration channel is used to determine that a cable has been disconnected from the power source. This charging system contains a capacitive power converter and a controller for controlling the capacitive power converter. There is also a configuration channel detector, which is arranged to detect the status of the configuration channel and to provide this status to the controller, so that the system can determine that the source has been detached from the bus when no configuration channel data is present.

Abstract: A low-dropout (LDO) regulator includes a voltage reference circuit to provide a reference voltage, a pass device including an input terminal coupled to a voltage input, an output terminal to provide an output voltage and a control terminal, and an error amplifier including a first amplifier input for receiving the reference voltage, a second amplifier input, an amplifier output coupled to the control terminal of the pass device. Additionally, the LDO regulator includes a feedback circuit including a feedback input coupled to the output terminal of the pass device and a feedback output coupled to the second amplifier input to provide a feedback signal. The LDO regulator further includes a control circuit including a non-volatile memory to store configuration data to control operation of the voltage reference circuit, the pass device, the error amplifier, and the feedback circuit to produce the output voltage.

Abstract: In an embodiment, a low-dropout (LDO) regulator includes at least one of a programmable voltage reference and a programmable frequency compensation circuit and is configurable to produce an output voltage. The programmable voltage reference includes a floating-gate transistor coupled to a reference output and configurable for providing a reference voltage to an input of an error amplifier. The programmable frequency compensation circuit is responsive to a programmable current reference circuit that includes at least one floating-gate transistor that is configurable to adjust a frequency compensation parameter. A control circuit is provided to selectively program floating gates of the floating gate transistors to adjust the output voltage and/or to adjust a frequency component of the output voltage.

Abstract: In an embodiment, a low-dropout (LDO) regulator includes at least one of a programmable voltage reference and a programmable frequency compensation circuit and is configurable to produce an output voltage. The programmable voltage reference includes a floating-gate transistor coupled to a reference output and configurable for providing a reference voltage to an input of an error amplifier. The programmable frequency compensation circuit is responsive to a programmable current reference circuit that includes at least one floating-gate transistor that is configurable to adjust a frequency compensation parameter. A control circuit is provided to selectively program floating gates of the floating gate transistors to adjust the output voltage and/or to adjust a frequency component of the output voltage.

Abstract: A low-dropout (LDO) regulator includes a voltage reference circuit to provide a reference voltage, a pass device including an input terminal coupled to a voltage input, an output terminal to provide an output voltage and a control terminal, and an error amplifier including a first amplifier input for receiving the reference voltage, a second amplifier input, an amplifier output coupled to the control terminal of the pass device. Additionally, the LDO regulator includes a feedback circuit including a feedback input coupled to the output terminal of the pass device and a feedback output coupled to the second amplifier input to provide a feedback signal. The LDO regulator further includes a control circuit including a non-volatile memory to store configuration data to control operation of the voltage reference circuit, the pass device, the error amplifier, and the feedback circuit to produce the output voltage.

Abstract: A non-volatile memory cell fabricated with a conventional CMOS process, including a flip-flop circuit having an NMOS transistor that shares a floating gate with a write PMOS capacitor and an erase PMOS capacitor. An erase function is implemented by inducing Fowler-Nordheim tunneling through the erase PMOS capacitor, thereby providing a positive charge on the floating gate. A write function is implemented by inducing Fowler-Nordheim tunneling through the NMOS transistor, thereby providing a negative charge on the floating gate. The write PMOS capacitor provides bias voltages during the erase and write operations. Prior to a read operation, the flip-flop circuit is reset. If the floating gate stores a positive charge, the NMOS transistor turns on, thereby switching the state of the flip-flop circuit. If the floating gate stores a negative charge, the NMOS transistor turns off, thereby leaving the flip-flop circuit in the reset state.

Abstract: According to some embodiments, a single-pin method of configuring a multi-bit state of a state machine of a circuit comprises: connecting a configuration resistor load having a configuration resistance to a single input pin of the integrated circuit; injecting a configuration current through the input pin and configuration resistor load; in response to injecting the current, generating a sequence of configuration signals indicative of a plurality of results of a plurality of comparisons of the configuration resistance to a plurality of predetermined thresholds, each result corresponding to a threshold; and configuring the multi-bit state of the state machine according to the sequence of configuration signals.

Abstract: A non-volatile memory cell fabricated with a conventional CMOS process, including a flip-flop circuit having an NMOS transistor that shares a floating gate with a write PMOS capacitor and an erase PMOS capacitor. An erase function is implemented by inducing Fowler-Nordheim tunneling through the erase PMOS capacitor, thereby providing a positive charge on the floating gate. A write function is implemented by inducing Fowler-Nordheim tunneling through the NMOS transistor, thereby providing a negative charge on the floating gate. The write PMOS capacitor provides bias voltages during the erase and write operations. Prior to a read operation, the flip-flop circuit is reset. If the floating gate stores a positive charge, the NMOS transistor turns on, thereby switching the state of the flip-flop circuit. If the floating gate stores a negative charge, the NMOS transistor turns off, thereby leaving the flip-flop circuit in the reset state.

Abstract: A voltage reference circuit provides a reference voltage that can be precisely programmed. The threshold voltage of a first non-volatile memory (NVM) transistor is programmed while coupled in parallel with a second NVM transistor. During programming, one or more capacitors are connected between the floating gate of the first NVM transistor and ground, and one or more capacitors are connected between the floating gate of the second NVM transistor and ground. The first and second NVM transistors are then coupled to a differential amplifier, which is used to generate a single-ended reference voltage in response to the programmed threshold voltage of the first NVM transistor. Bipolar transistors are selectively switched between the various capacitors and ground, thereby providing precise adjustment of the temperature coefficient of the voltage reference circuit.

Abstract: A voltage reference circuit provides a reference voltage that can be precisely programmed. The threshold voltage of a first non-volatile memory (NVM) transistor is programmed while coupled in parallel with a second NVM transistor. During programming, one or more capacitors are connected between the floating gate of the first NVM transistor and ground, and one or more capacitors are connected between the floating gate of the second NVM transistor and ground. The first and second NVM transistors are then coupled to a differential amplifier, which is used to generate a single-ended reference voltage in response to the programmed threshold voltage of the first NVM transistor. Bipolar transistors are selectively switched between the various capacitors and ground, thereby providing precise adjustment of the temperature coefficient of the voltage reference circuit.

Abstract: A voltage reference circuit provides a reference voltage that can be precisely programmed. The threshold voltage of a first non-volatile memory (NVM) transistor is programmed while coupled in parallel with a reference NVM transistor. During programming, the reference NVM transistor has a floating gate coupled to ground through a first set of capacitors, and coupled to a reference voltage through a second set of capacitors. The program threshold voltage of the first NVM transistor is dependent on the first and second sets of capacitors. The first and reference NVM transistors are then coupled in parallel, and a differential amplifier is used to generate a single-ended reference voltage in response to the programmed threshold voltage of the first NVM transistor. Capacitors can be transferred between the first set and the second set, thereby providing precise adjustment of the single ended reference voltage.