Patents by Inventor Sabin Eftimie

Sabin Eftimie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10530249
    Abstract: Power converters, charge pumps and methods which are capable of regulating output voltage are presented. A power converter has a capacitive element, a first transistor, a second transistor, a third transistor, and a fourth transistor. The first transistor is coupled between an input terminal and a first terminal of the capacitve element. The second transistor is coupled between the first terminal of the capacitve element and an output terminal. The third transistor is coupled between the output terminal and a second terminal of the capacitive element. The fourth transistor is coupled between the second terminal of the capacitive element and a reference potential. The power converter has a control circuit to control, during a first time interval of a voltage regulation mode, one of the four transistors such that the one of the four transistors is operated as a controllable power source for regulating an output voltage.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: January 7, 2020
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Jong Lee, Sabin Eftimie
  • Patent number: 10461555
    Abstract: A wired connection, such as USB-C, for charging a sink from a source, has a configuration channel and a power transmission channel. The presence of data on the configuration channel is used to determine that a cable has been disconnected from the power source. This charging system contains a capacitive power converter and a controller for controlling the capacitive power converter. There is also a configuration channel detector, which is arranged to detect the status of the configuration channel and to provide this status to the controller, so that the system can determine that the source has been detached from the bus when no configuration channel data is present.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: October 29, 2019
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Sabin Eftimie, Lasse Harju, Manfred Kogler, Amit Bavisi, Sorin Negru
  • Publication number: 20180337541
    Abstract: A wired connection, such as USB-C, for charging a sink from a source, has a configuration channel and a power transmission channel. The presence of data on the configuration channel is used to determine that a cable has been disconnected from the power source. This charging system contains a capacitive power converter and a controller for controlling the capacitive power converter. There is also a configuration channel detector, which is arranged to detect the status of the configuration channel and to provide this status to the controller, so that the system can determine that the source has been detached from the bus when no configuration channel data is present.
    Type: Application
    Filed: May 18, 2017
    Publication date: November 22, 2018
    Inventors: Sabin Eftimie, Lasse Harju, Manfred Kogler, Amit Bavisi, Sorin Negru
  • Patent number: 9411348
    Abstract: A low-dropout (LDO) regulator includes a voltage reference circuit to provide a reference voltage, a pass device including an input terminal coupled to a voltage input, an output terminal to provide an output voltage and a control terminal, and an error amplifier including a first amplifier input for receiving the reference voltage, a second amplifier input, an amplifier output coupled to the control terminal of the pass device. Additionally, the LDO regulator includes a feedback circuit including a feedback input coupled to the output terminal of the pass device and a feedback output coupled to the second amplifier input to provide a feedback signal. The LDO regulator further includes a control circuit including a non-volatile memory to store configuration data to control operation of the voltage reference circuit, the pass device, the error amplifier, and the feedback circuit to produce the output voltage.
    Type: Grant
    Filed: April 13, 2010
    Date of Patent: August 9, 2016
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Radu H. Iacob, Cornel D. Stanescu, Adrian M. Tache, Sabin A. Eftimie
  • Patent number: 8400126
    Abstract: In an embodiment, a low-dropout (LDO) regulator includes at least one of a programmable voltage reference and a programmable frequency compensation circuit and is configurable to produce an output voltage. The programmable voltage reference includes a floating-gate transistor coupled to a reference output and configurable for providing a reference voltage to an input of an error amplifier. The programmable frequency compensation circuit is responsive to a programmable current reference circuit that includes at least one floating-gate transistor that is configurable to adjust a frequency compensation parameter. A control circuit is provided to selectively program floating gates of the floating gate transistors to adjust the output voltage and/or to adjust a frequency component of the output voltage.
    Type: Grant
    Filed: April 14, 2010
    Date of Patent: March 19, 2013
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Radu H. Iacob, Sabin A. Eftimie, Cornel D. Stanescu, Andreea Creosteanu, Marian Badila
  • Publication number: 20110254521
    Abstract: In an embodiment, a low-dropout (LDO) regulator includes at least one of a programmable voltage reference and a programmable frequency compensation circuit and is configurable to produce an output voltage. The programmable voltage reference includes a floating-gate transistor coupled to a reference output and configurable for providing a reference voltage to an input of an error amplifier. The programmable frequency compensation circuit is responsive to a programmable current reference circuit that includes at least one floating-gate transistor that is configurable to adjust a frequency compensation parameter. A control circuit is provided to selectively program floating gates of the floating gate transistors to adjust the output voltage and/or to adjust a frequency component of the output voltage.
    Type: Application
    Filed: April 14, 2010
    Publication date: October 20, 2011
    Inventors: Radu H. Iacob, Sabin A. Eftimie, Cornel D. Stanescu, Andreea Creosteanu, Marian Badila
  • Publication number: 20110248688
    Abstract: A low-dropout (LDO) regulator includes a voltage reference circuit to provide a reference voltage, a pass device including an input terminal coupled to a voltage input, an output terminal to provide an output voltage and a control terminal, and an error amplifier including a first amplifier input for receiving the reference voltage, a second amplifier input, an amplifier output coupled to the control terminal of the pass device. Additionally, the LDO regulator includes a feedback circuit including a feedback input coupled to the output terminal of the pass device and a feedback output coupled to the second amplifier input to provide a feedback signal. The LDO regulator further includes a control circuit including a non-volatile memory to store configuration data to control operation of the voltage reference circuit, the pass device, the error amplifier, and the feedback circuit to produce the output voltage.
    Type: Application
    Filed: April 13, 2010
    Publication date: October 13, 2011
    Inventors: Radu H. Iacob, Cornel D. Stanescu, Adrian M. Tache, Sabin A. Eftimie
  • Patent number: 7558111
    Abstract: A non-volatile memory cell fabricated with a conventional CMOS process, including a flip-flop circuit having an NMOS transistor that shares a floating gate with a write PMOS capacitor and an erase PMOS capacitor. An erase function is implemented by inducing Fowler-Nordheim tunneling through the erase PMOS capacitor, thereby providing a positive charge on the floating gate. A write function is implemented by inducing Fowler-Nordheim tunneling through the NMOS transistor, thereby providing a negative charge on the floating gate. The write PMOS capacitor provides bias voltages during the erase and write operations. Prior to a read operation, the flip-flop circuit is reset. If the floating gate stores a positive charge, the NMOS transistor turns on, thereby switching the state of the flip-flop circuit. If the floating gate stores a negative charge, the NMOS transistor turns off, thereby leaving the flip-flop circuit in the reset state.
    Type: Grant
    Filed: September 1, 2006
    Date of Patent: July 7, 2009
    Assignee: Catalyst Semiconductor, Inc.
    Inventors: Sabin A. Eftimie, Ilie Marian I. Poenaru, Sorin S. Georgescu
  • Publication number: 20080278346
    Abstract: According to some embodiments, a single-pin method of configuring a multi-bit state of a state machine of a circuit comprises: connecting a configuration resistor load having a configuration resistance to a single input pin of the integrated circuit; injecting a configuration current through the input pin and configuration resistor load; in response to injecting the current, generating a sequence of configuration signals indicative of a plurality of results of a plurality of comparisons of the configuration resistance to a plurality of predetermined thresholds, each result corresponding to a threshold; and configuring the multi-bit state of the state machine according to the sequence of configuration signals.
    Type: Application
    Filed: May 11, 2007
    Publication date: November 13, 2008
    Inventors: Sabin A. Eftimie, Sorin S. Georgescu, Alexandra A. Epure
  • Publication number: 20080055965
    Abstract: A non-volatile memory cell fabricated with a conventional CMOS process, including a flip-flop circuit having an NMOS transistor that shares a floating gate with a write PMOS capacitor and an erase PMOS capacitor. An erase function is implemented by inducing Fowler-Nordheim tunneling through the erase PMOS capacitor, thereby providing a positive charge on the floating gate. A write function is implemented by inducing Fowler-Nordheim tunneling through the NMOS transistor, thereby providing a negative charge on the floating gate. The write PMOS capacitor provides bias voltages during the erase and write operations. Prior to a read operation, the flip-flop circuit is reset. If the floating gate stores a positive charge, the NMOS transistor turns on, thereby switching the state of the flip-flop circuit. If the floating gate stores a negative charge, the NMOS transistor turns off, thereby leaving the flip-flop circuit in the reset state.
    Type: Application
    Filed: September 1, 2006
    Publication date: March 6, 2008
    Applicant: Catalyst Semiconductor, Inc.
    Inventors: Sabin A. Eftimie, Ilie Marian I. Poenaru, Sorin S. Georgescu
  • Patent number: 7324380
    Abstract: A voltage reference circuit provides a reference voltage that can be precisely programmed. The threshold voltage of a first non-volatile memory (NVM) transistor is programmed while coupled in parallel with a second NVM transistor. During programming, one or more capacitors are connected between the floating gate of the first NVM transistor and ground, and one or more capacitors are connected between the floating gate of the second NVM transistor and ground. The first and second NVM transistors are then coupled to a differential amplifier, which is used to generate a single-ended reference voltage in response to the programmed threshold voltage of the first NVM transistor. Bipolar transistors are selectively switched between the various capacitors and ground, thereby providing precise adjustment of the temperature coefficient of the voltage reference circuit.
    Type: Grant
    Filed: December 15, 2006
    Date of Patent: January 29, 2008
    Assignee: Catalyst Semiconductor, Inc.
    Inventors: Alina I. Negut, Sorin S. Georgescu, Sabin A. Eftimie
  • Publication number: 20070189069
    Abstract: A voltage reference circuit provides a reference voltage that can be precisely programmed. The threshold voltage of a first non-volatile memory (NVM) transistor is programmed while coupled in parallel with a second NVM transistor. During programming, one or more capacitors are connected between the floating gate of the first NVM transistor and ground, and one or more capacitors are connected between the floating gate of the second NVM transistor and ground. The first and second NVM transistors are then coupled to a differential amplifier, which is used to generate a single-ended reference voltage in response to the programmed threshold voltage of the first NVM transistor. Bipolar transistors are selectively switched between the various capacitors and ground, thereby providing precise adjustment of the temperature coefficient of the voltage reference circuit.
    Type: Application
    Filed: December 15, 2006
    Publication date: August 16, 2007
    Applicant: Catalyst Semiconductor, Inc.
    Inventors: Alina I. Negut, Sorin S. Georgescu, Sabin A. Eftimie
  • Patent number: 7245536
    Abstract: A voltage reference circuit provides a reference voltage that can be precisely programmed. The threshold voltage of a first non-volatile memory (NVM) transistor is programmed while coupled in parallel with a reference NVM transistor. During programming, the reference NVM transistor has a floating gate coupled to ground through a first set of capacitors, and coupled to a reference voltage through a second set of capacitors. The program threshold voltage of the first NVM transistor is dependent on the first and second sets of capacitors. The first and reference NVM transistors are then coupled in parallel, and a differential amplifier is used to generate a single-ended reference voltage in response to the programmed threshold voltage of the first NVM transistor. Capacitors can be transferred between the first set and the second set, thereby providing precise adjustment of the single ended reference voltage.
    Type: Grant
    Filed: February 15, 2006
    Date of Patent: July 17, 2007
    Assignee: Catalyst Semiconductor, Inc.
    Inventors: Ilie Marian I. Poenaru, Sabin A. Eftimie, Sorin S. Georgescu