Patents by Inventor Sachin Idgunji

Sachin Idgunji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160349827
    Abstract: A power-gating array configured to power gate a logic block includes multiple zones of sleep field-effect transistors (FETs). A zone controller coupled to the power-gating array selectively enables a certain number of zones within the array depending on the voltage drawn by the logic block. When the logic block draws a lower voltage, the zone controller enables a lower number of zones. When the logic block draws a higher voltage, the zone controller enables a greater number of zones. One advantage of the disclosed technique is that sleep FET usage is reduced, thereby countering the effects of FET deterioration due to BTI and TDDB. Accordingly, the lifetime of sleep FETs configured to perform power gating for logic blocks may be extended.
    Type: Application
    Filed: May 26, 2015
    Publication date: December 1, 2016
    Inventors: Sachin IDGUNJI, Tezaswi RAJA
  • Publication number: 20160041814
    Abstract: A true random number generator, a method of generating a true random number and a system incorporating the generator or the method. In one embodiment, the generator includes: (1) a ring oscillator including inverting gates having power inputs and (2) a time-varying power supply coupled to the power inputs to provide power thereto and including power perturbation circuitry operable to perturb the power provided to at least one of the power inputs.
    Type: Application
    Filed: October 22, 2015
    Publication date: February 11, 2016
    Inventor: Sachin Idgunji
  • Patent number: 9195434
    Abstract: A true random number generator, a method of generating a true random number and a system incorporating the generator or the method. In one embodiment, the generator includes: (1) a ring oscillator including inverting gates having power inputs and (2) a time-varying power supply coupled to the power inputs to provide power thereto and including power perturbation circuitry operable to perturb the power provided to at least one of the power inputs.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: November 24, 2015
    Assignee: Nvidia Corporation
    Inventor: Sachin Idgunji
  • Publication number: 20150199176
    Abstract: A true random number generator, a method of generating a true random number and a system incorporating the generator or the method. In one embodiment, the generator includes: (1) a ring oscillator including inverting gates having power inputs and (2) a time-varying power supply coupled to the power inputs to provide power thereto and including power perturbation circuitry operable to perturb the power provided to at least one of the power inputs.
    Type: Application
    Filed: January 14, 2014
    Publication date: July 16, 2015
    Applicant: Nvidia Corporation
    Inventor: Sachin Idgunji