Patents by Inventor Sadagopan Srinivasan
Sadagopan Srinivasan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10664039Abstract: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.Type: GrantFiled: July 24, 2018Date of Patent: May 26, 2020Assignee: Intel CorporationInventors: Andrew J. Herdrich, Rameshkumar G. Illikkal, Ravishankar Iyer, Sadagopan Srinivasan, Jaideep Moses, Srihari Makineni
-
Publication number: 20180329478Abstract: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.Type: ApplicationFiled: July 24, 2018Publication date: November 15, 2018Inventors: Andrew J. Herdrich, Rameshkumar G. Illikkal, Ravishankar Iyer, Sadagopan Srinivasan, Jaideep Moses, Srihari Makineni
-
Patent number: 10048743Abstract: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.Type: GrantFiled: April 21, 2016Date of Patent: August 14, 2018Assignee: Intel CorporationInventors: Andrew J. Herdrich, Rameshkumar G. Illikkal, Ravishankar Iyer, Sadagopan Srinivasan, Jaideep Moses, Srihari Makineni
-
Publication number: 20180039518Abstract: In an illustrative example, a system includes a resource and a first processor. The first processor is configured to access the resource based on a first physical address space and to generate a request for access to the resource. The request has a first format. The system further includes a second processor configured to access the resource based on a second physical address space. The system also includes a device coupled to the resource and to the first processor. The device is configured to receive the request, to generate a message having a second format based on the request, to send the message to the resource, and to provide a reply to the request to the first processor.Type: ApplicationFiled: August 2, 2016Publication date: February 8, 2018Inventors: Ramkumar Jayaseelan, Sadagopan Srinivasan, Thomas Andrew Hartin
-
Patent number: 9870047Abstract: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.Type: GrantFiled: June 24, 2016Date of Patent: January 16, 2018Assignee: Intel CorporationInventors: Andrew J. Herdrich, Rameshkumar G. Illikkal, Ravishankar Iyer, Sadagopan Srinivasan, Jaideep Moses, Srihari Makineni
-
Patent number: 9864427Abstract: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.Type: GrantFiled: April 21, 2016Date of Patent: January 9, 2018Assignee: Intel CorporationInventors: Andrew J. Herdrich, Rameshkumar G. Illikkal, Ravishankar Iyer, Sadagopan Srinivasan, Jaideep Moses, Srihari Makineni
-
Publication number: 20170371564Abstract: Methods and apparatus monitor memory access activities of non-real-time processing engines to determine time intervals when the memory access activities are low. When such time intervals are found, the methods and apparatus perform burst memory access control for real-time processing engines by bursting data from a memory to a burst memory buffer, or from the burst memory buffer to the memory, to allow fast data access by the real-time processing engines.Type: ApplicationFiled: June 28, 2016Publication date: December 28, 2017Inventors: Shuzhi Hou, Sadagopan Srinivasan, Daniel L. Bouvier
-
Publication number: 20170337084Abstract: An apparatus includes a set of one or more processing cores, a thread dispatcher, and an event register of a first compute unit. The set of one or more processing cores is configured to execute a set of threads. The thread dispatcher is coupled to the set of one or more processing cores and is configured to select threads of the set of threads for execution by the set of one or more processing cores. The thread dispatcher is further configured to refrain from selecting a first thread of the set of threads for execution in response to a first value of one or more bits of the event register and to select the first thread for execution in response to a second value of the one or more bits.Type: ApplicationFiled: May 18, 2016Publication date: November 23, 2017Inventors: Ramkumar Jayaseelan, Raghuram S. Tupuri, Sadagopan Srinivasan, Thomas Andrew Hartin
-
Publication number: 20160306415Abstract: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.Type: ApplicationFiled: June 24, 2016Publication date: October 20, 2016Inventors: Andrew J. Herdrich, Rameshkumar G. Illikkal, Ravishankar Iyer, Sadagopan Srinivasan, Jaideep Moses, Srihari Makineni
-
Publication number: 20160132354Abstract: Methods and apparatus to schedule applications in heterogeneous multiprocessor computing platforms are described. In one embodiment, information regarding performance (e.g., execution performance and/or power consumption performance) of a plurality of processor cores of a processor is stored (and tracked) in counters and/or tables. Logic in the processor determines which processor core should execute an application based on the stored information. Other embodiments are also claimed and disclosed.Type: ApplicationFiled: January 13, 2016Publication date: May 12, 2016Inventors: Ravishankar Iyer, Sadagopan Srinivasan, LI ZHAO, Rameshkumar G. Illikkal
-
Patent number: 9268611Abstract: Methods and apparatus to schedule applications in heterogeneous multiprocessor computing platforms are described. In one embodiment, information regarding performance (e.g., execution performance and/or power consumption performance) of a plurality of processor cores of a processor is stored (and tracked) in counters and/or tables. Logic in the processor determines which processor core should execute an application based on the stored information. Other embodiments are also claimed and disclosed.Type: GrantFiled: September 25, 2010Date of Patent: February 23, 2016Assignee: Intel CorporationInventors: Ravishankar Iyer, Sadagopan Srinivasan, Li Zhao, Rameshkumar G. Illikkal
-
Publication number: 20150363116Abstract: A processor monitors, directly or indirectly, the amount of time it takes for the memory controller to respond to one or more memory access requests. When this memory access latency indicates that a memory latency tolerance of a program thread has been exceeded, the processor can apportion additional power to the memory controller, thereby increasing the speed with which the memory controller can process memory access requests.Type: ApplicationFiled: June 12, 2014Publication date: December 17, 2015Inventors: Sibi Govindan, Sadagopan Srinivasan, Lloyd Bircher
-
Patent number: 9201500Abstract: Systems and methods may provide for capturing a user input by emulating a touch screen mechanism. In one example, the method may include identifying a point of interest on a front facing display of the device based on gaze information associated with a user of the device, identifying a hand action based on gesture information associated with the user of the device, and initiating a device action with respect to the front facing display based on the point of interest and the hand action.Type: GrantFiled: September 28, 2012Date of Patent: December 1, 2015Assignee: Intel CorporationInventors: Sadagopan Srinivasan, Rameshkumar Illikkal, Ravishankar Iyer
-
Patent number: 9128842Abstract: A processor is described having cache circuitry and logic circuitry. The logic circuitry is to manage the entry and removal of cache lines from the cache circuitry. The logic circuitry includes storage circuitry and control circuitry. The storage circuitry is to store information identifying a set of cache lines within the cache that are in a modified state. The control circuitry is coupled to the storage circuitry to receive the information from the storage circuitry, responsive to a signal to flush the cache, and determine addresses of the cache therefrom so that the set of cache lines are read from the cache so as to avoid reading cache lines from the cache that are in an invalid or a clean state.Type: GrantFiled: September 28, 2012Date of Patent: September 8, 2015Assignee: Intel CorporationInventors: Jaideep Moses, Ravishankar Iyer, Rameshkumar G. Illikkal, Sadagopan Srinivasan
-
Patent number: 8984311Abstract: Embodiments of systems, apparatuses, and methods for energy-efficient operation of a device are described. In some embodiments, a cache performance indicator of a cache is monitored, and a set of one or more cache performance parameters based on the cache performance indicator is determined. The cache is dynamically resized to an optimal cache size based on a comparison of the cache performance parameters to their energy-efficient targets to reduce power consumption.Type: GrantFiled: December 30, 2011Date of Patent: March 17, 2015Assignee: Intel CorporationInventors: Jaideep Moses, Rameshkumar G. Illikkal, Ravishankar Iyer, Jared E. Bendt, Sadagopan Srinivasan, Andrew J. Herdrich, Ashish V. Choubal, Avinash N. Ananthakrishnan, Vijay S. R. Degalahal
-
Patent number: 8861847Abstract: A system and method for detecting human skin tone in one or more images. The system includes an image processing module configured to receive an image and provide contrast enhancement of the image so as to compensate for background illumination in the image. The image processing module is further configured to detect and identify regions of the contrast-enhanced image containing human skin tone based, at least in part, on the utilization of multiple color spaces and adaptively generated thresholds for each color space. A system and method consistent with the present disclosure is configure to provide accurate detection of human skin tone while accounting for variations in skin appearance due to a variety of factors, including background illumination and objects.Type: GrantFiled: December 21, 2012Date of Patent: October 14, 2014Assignee: Intel CorporationInventors: Sadagopan Srinivasan, Michael E. Kounavis, Rameshkumar G. Illikkal, Ravishankar Iyer
-
Publication number: 20140177955Abstract: A system and method for detecting human skin tone in one or more images. The system includes an image processing module configured to receive an image and provide contrast enhancement of the image so as to compensate for background illumination in the image. The image processing module is further configured to detect and identify regions of the contrast-enhanced image containing human skin tone based, at least in part, on the utilization of multiple color spaces and adaptively generated thresholds for each color space. A system and method consistent with the present disclosure is configure to provide accurate detection of human skin tone while accounting for variations in skin appearance due to a variety of factors, including background illumination and objects.Type: ApplicationFiled: December 21, 2012Publication date: June 26, 2014Inventors: Sadagopan Srinivasan, Michael E. Kounavis, Rameshkumar G. Illikkal, Ravishankar Iyer
-
Publication number: 20140095794Abstract: A processor is described having cache circuitry and logic circuitry. The logic circuitry is to manage the entry and removal of cache lines from the cache circuitry. The logic circuitry includes storage circuitry and control circuitry. The storage circuitry is to store information identifying a set of cache lines within the cache that are in a modified state. The control circuitry is coupled to the storage circuitry to receive the information from the storage circuitry, responsive to a signal to flush the cache, and determine addresses of the cache therefrom so that the set of cache lines are read from the cache so as to avoid reading cache lines from the cache that are in an invalid or a clean state.Type: ApplicationFiled: September 28, 2012Publication date: April 3, 2014Inventors: Jaideep MOSES, Ravishankar IYER, Ramesh G. ILLIKKAL, Sadagopan SRINIVASAN
-
Publication number: 20140092014Abstract: Systems and methods may provide for capturing a user input by emulating a touch screen mechanism. In one example, the method may include identifying a point of interest on a front facing display of the device based on gaze information associated with a user of the device, identifying a hand action based on gesture information associated with the user of the device, and initiating a device action with respect to the front facing display based on the point of interest and the hand action.Type: ApplicationFiled: September 28, 2012Publication date: April 3, 2014Inventors: Sadagopan Srinivasan, Rameshkumar Illikkal, Ravishankar Iyer
-
Patent number: 8649262Abstract: According to some embodiments, first and second processing elements may be provided on a die, and there may be a plurality of potential communication links between the first and second processing elements. Moreover, control logic may be provided on the die to dynamically activate at least some of the potential communication links (e.g., based on a current bandwidth appropriate between the first and second processing elements).Type: GrantFiled: September 30, 2008Date of Patent: February 11, 2014Assignee: Intel CorporationInventors: Sadagopan Srinivasan, Michael W. Leddige, Bin Li, Michael Espig