Patents by Inventor Sadagopan Srinivasan

Sadagopan Srinivasan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8412885
    Abstract: In an embodiment of the present invention a method includes: sending request for data to a memory controller; arranging the request for data by order of importance or priority; identifying a source of the request for data; and if the source is an input/output device, masking off P ways in a cache; and allocating ways in filling the cache. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 12, 2009
    Date of Patent: April 2, 2013
    Assignee: Intel Corporation
    Inventors: Liqun Cheng, Zhen Fang, Jeffrey Wilder, Sadagopan Srinivasan, Ravishankar Iyer, Donald Newell
  • Publication number: 20120173907
    Abstract: Embodiments of systems, apparatuses, and methods for energy-efficient operation of a device are described. In some embodiments, a cache performance indicator of a cache is monitored, and a set of one or more cache performance parameters based on the cache performance indicator is determined. The cache is dynamically resized to an optimal cache size based on a comparison of the cache performance parameters to their energy-efficient targets to reduce power consumption.
    Type: Application
    Filed: December 30, 2011
    Publication date: July 5, 2012
    Inventors: Jaideep MOSES, Rameshkumar G. Illikkal, Ravishankar Iyer, Jared E. Bendt, Sadagopan Srinivasan, Andrew J. Herdrich, Ashish V. Choubal, Avinash N. Ananthakrishnan, Vijay S.R. Degalahal
  • Publication number: 20120079235
    Abstract: Methods and apparatus to schedule applications in heterogeneous multiprocessor computing platforms are described. In one embodiment, information regarding performance (e.g., execution performance and/or power consumption performance) of a plurality of processor cores of a processor is stored (and tracked) in counters and/or tables. Logic in the processor determines which processor core should execute an application based on the stored information. Other embodiments are also claimed and disclosed.
    Type: Application
    Filed: September 25, 2010
    Publication date: March 29, 2012
    Inventors: Ravishankar Iyer, Sadagopan Srinivasan, Li Zhao, Rameshkumar G. Illikkal
  • Publication number: 20110113198
    Abstract: The present invention discloses a method comprising: sending request for data to a memory controller; arranging the request for data by order of importance or priority; identifying a source of the request for data; if the source is an input/output device, masking off P ways in a cache; and allocating ways in filling the cache. The method further includes extending cache allocation logic to control a tag comparison operation by using a bit to provide a hint from IO devices that certain ways will not have requested data.
    Type: Application
    Filed: November 12, 2009
    Publication date: May 12, 2011
    Inventors: Liqun Cheng, Zhen Fang, Jeffrey Wilder, Sadagopan Srinivasan, Ravishankar Iyer, Donald Newell
  • Publication number: 20100080132
    Abstract: According to some embodiments, first and second processing elements may be provided on a die, and there may be a plurality of potential communication links between the first and second processing elements. Moreover, control logic may be provided on the die to dynamically activate at least some of the potential communication links (e.g., based on a current bandwidth appropriate between the first and second processing elements).
    Type: Application
    Filed: September 30, 2008
    Publication date: April 1, 2010
    Inventors: Sadagopan Srinivasan, Michael W. Leddige, Bin Li, Michael Espig