Patents by Inventor Sadahiko Miura

Sadahiko Miura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040052127
    Abstract: A magnetic random access memory is provided including a substrate, a magnetoresistance element which includes a ferromagnetic layer having an invertible spontaneous magnetization, which varies in resistance according to the direction of the spontaneous magnetization, and is formed above the substrate, and a wiring which extends in a first direction and is used for making an electric current flow to generate a magnetic field to be applied to the magnetoresistance element. The wiring is formed so as to pass through a first position which is closer to the substrate than the magnetoresistance element and does not overlap the magnetoresistance element when viewed from a direction perpendicular to the main surface of the substrate, and a second position being above said magnetoresistance element.
    Type: Application
    Filed: September 11, 2003
    Publication date: March 18, 2004
    Applicant: NEC CORPORATION
    Inventors: Tetsuhiro Suzuki, Sadahiko Miura
  • Patent number: 6191972
    Abstract: A magnetic random access memory circuit comprises first and second row decoders receiving a part of a given address, first and second column decoders receiving the other part of a given address, a plurality of pairs of sense lines connected between output terminals of the first row decoder and output terminals of the second row decoder, each pair of sense lines being located adjacent to each other, a plurality of word lines connected between output terminals of the first column decoder and output terminals of the second column decoder, and extending to intersect the sense lines so that intersections of the sense lines and the word lines are located in the form of a matrix. A memory array includes a plurality of cell pairs distributed over the matrix, each cell pair including a memory cell and a reference cell located adjacent to each other. Each of the memory cell and the reference cell includes a magneto-resistive element.
    Type: Grant
    Filed: May 1, 2000
    Date of Patent: February 20, 2001
    Assignee: NEC Corporation
    Inventors: Sadahiko Miura, Hideaki Numata
  • Patent number: 6163713
    Abstract: In a high frequency transmission line having a dielectric substrate and a conductor line which is provided on the dielectric substrate for allowing electric current to flow therethrough, the conductor line has a non-grain-boundary oxide superconductor layer with twin walls but without grain boundaries. The high frequency transmission line is in the form of a plane circuit. It is preferable that an oriented oxide superconductor layer is provided between the dielectric substrate and the non-grain-boundary oxide superconductor layer.
    Type: Grant
    Filed: March 5, 1998
    Date of Patent: December 19, 2000
    Assignees: NEC Corporation, Sumitomo Electric Industries, Ltd., International Superconductivity Technology Center
    Inventors: Katsumi Suzuki, Sadahiko Miura, Takayuki Inoue, Koji Muranaka, Hideaki Zama, Youichi Enomoto, Tadataka Morishita, Shoji Tanaka
  • Patent number: 6014575
    Abstract: The present invention provides a superconducting transmission delay line phase shifter which has an essential structure as follows. The superconducting transmission delay line phase shifter has a layer made of a material showing a low dielectric loss the layer comprising first, second and third sections, wherein the second section being positioned between the first and third sections. The superconducting transmission delay line phase shifter also has a ferroelectric selectively provided in the second section. The ferroelectric extends between boundaries of the second section to the first and third sections. The superconducting transmission delay line phase shifter also has a thin film made of a conductor having a high conductivity. The conductive thin film extends across the bottoms of the first, second and third sections. The superconducting transmission delay line phase shifter also has a superconducting signal transmission line, on which signals are transmitted.
    Type: Grant
    Filed: October 27, 1995
    Date of Patent: January 11, 2000
    Assignee: NEC Corporation
    Inventor: Sadahiko Miura
  • Patent number: 6008162
    Abstract: The present invention can provide an oxide superconductive film with a smooth surface and at homogeneous thickness on a simple substrate structure at a high film formation rate. In a liquid phase epitaxial growth method for producing an ReBa.sub.2 Cu.sub.3 Ox film (3) (Rerepresents one selected from lanthanoids such as Y and Nd, and X represents the oxygen amount) having a 123 type crystal structure from a molten liquid (1), a substrate (2) surface is inclined by 1 degree to 44 degrees with respect to the molten liquid surface at the time of separating the film from the molten liquid after film formation. After separating the film from the molten liquid, the substrate is rotated at 300 rpm to 3000 rpm for 5 seconds to 5 minutes. The film formation atmosphere contains 2 at. % of oxygen and 98 at. % of nitrogen, and the film formation temperature is 900 to 970.degree. C.
    Type: Grant
    Filed: March 31, 1998
    Date of Patent: December 28, 1999
    Assignees: NEC Corporation, International Conductivity Technology Center
    Inventors: Sadahiko Miura, Tadataka Morishita, Youichi Enomoto
  • Patent number: 5084438
    Abstract: An electronic device substrate includes a spinel epitaxial film formed on a silicon single-crystal substrate and an oxide superconductor layer formed on the spinel film. The oxide superconductor layer is represented by formula P.sub.x (Q,Ca).sub.y Cu.sub.z O.sub..delta. and contains at least one element of Bi and Tl as P and at least one element of Sr and Ba as Q. Composition ratios fall within ranges of 0.08.ltoreq.x/(x+y+z).ltoreq.0.41, 0.29.ltoreq.y/(x+y+z).ltoreq.0.47 and 1.ltoreq.Q/Ca.ltoreq.3.
    Type: Grant
    Filed: March 21, 1989
    Date of Patent: January 28, 1992
    Assignee: NEC Corporation
    Inventors: Shogo Matsubara, Yoichi Miyasaka, Sadahiko Miura