Patents by Inventor Sadahiro Kato

Sadahiro Kato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200108378
    Abstract: Provide is a functional structural body that can suppress aggregation of metal oxide nanoparticles and prevent functional loss of metal oxide nanoparticles, and thus exhibit a stable function over a long period of time. A functional structural body (1) includes: a skeletal body (10) of a porous structure composed of a zeolite-type compound; and at least one type of metal oxide nanoparticles (20) containing a perovskite-type oxide present in the skeletal body (10), the skeletal body (10) having channels (11) that connect with each other, and the metal oxide nanoparticles (20) being present at least in the channels (11) of the skeletal body (10).
    Type: Application
    Filed: November 27, 2019
    Publication date: April 9, 2020
    Inventors: Takao MASUDA, Yuta NAKASAKA, Takuya YOSHIKAWA, Sadahiro KATO, Masayuki FUKUSHIMA, Kojiro INAMORI, Hiroko TAKAHASHI, Yuichiro BANBA, Kaori SEKINE
  • Publication number: 20200108374
    Abstract: A functional structural body includes a skeletal body of a porous structure composed of a zeolite-type compound, and at least one type of metallic nanoparticles present in the skeletal body, the skeletal body having channels connecting with each other, the metallic nanoparticles being present at least in the channels of the skeletal body.
    Type: Application
    Filed: November 27, 2019
    Publication date: April 9, 2020
    Inventors: Takao MASUDA, Yuta NAKASAKA, Takuya YOSHIKAWA, Sadahiro KATO, Masayuki FUKUSHIMA, Kojiro INAMORI, Hiroko TAKAHASHI, Yuichiro BANBA, Kaori SEKINE
  • Publication number: 20200094232
    Abstract: A structured catalyst for steam reforming of the present disclosure is used for producing reformed gas containing hydrogen from a reforming raw material containing hydrocarbon, and includes a support having a porous structure constituted of a zeolite-type compound, and at least one catalytic substance present inside the support. The support includes channels connecting with each other, and the catalytic substance is metal nanoparticles and present at least in the channels of the support.
    Type: Application
    Filed: November 27, 2019
    Publication date: March 26, 2020
    Inventors: Takao MASUDA, Yuta NAKASAKA, Takuya YOSHIKAWA, Sadahiro KATO, Masayuki FUKUSHIMA, Hiroko TAKAHASHI, Yuichiro BANBA, Kaori SEKINE
  • Publication number: 20200094229
    Abstract: To provide a structured catalyst for catalytic cracking or hydrodesulfurization that suppresses decline in catalytic activity, achieves efficient catalytic cracking, and allows simple and stable obtaining of a substance to be modified. The structured catalyst for catalytic cracking or hydrodesulfurization (1) includes a support (10) of a porous structure composed of a zeolite-type compound and at least one type of metal oxide nanoparticles (20) present in the support (10), in which the support (10) has channels (11) that connect with each other, the metal oxide nanoparticles (20) are present at least in the channels (11) of the support (10), and the metal oxide nanoparticles (20) are composed of a material containing any one or two more of the oxides of Fe, Al, Zn, Zr, Cu, Co, Ni, Ce, Nb, Ti, Mo, V, Cr, Pd, and Ru.
    Type: Application
    Filed: November 27, 2019
    Publication date: March 26, 2020
    Inventors: Takao MASUDA, Yuta NAKASAKA, Takuya YOSHIKAWA, Sadahiro KATO, Masayuki FUKUSHIMA, Hiroko TAKAHASHI, Yuichiro BANBA, Kaori SEKINE
  • Publication number: 20190039056
    Abstract: A catalyst structure includes a carrier having a porous structure composed of a zeolite type compound and at least one catalytic material existing in the carrier. The carrier has channels communicating with each other, and the catalytic material is a metal fine particle and exists at least in the channel of the carrier.
    Type: Application
    Filed: May 31, 2018
    Publication date: February 7, 2019
    Applicant: Furukawa Electric Co., Ltd.
    Inventors: Sadahiro Kato, Masayuki Fukushima, Hiroko Takahashi, Yuichiro Banba, Kaori Sekine
  • Patent number: 8884393
    Abstract: A nitride compound semiconductor device includes: a substrate; a buffer layer formed on the substrate and including a plurality of composite layers each layered of: a first layer formed of a nitride compound semiconductor; and a second layer formed of a nitride compound semiconductor containing aluminum and having a lattice constant smaller than a lattice constant of the first layer; a semiconductor operating layer formed on the buffer layer; and a plurality of electrodes formed on the semiconductor operating layer. At least one of the second layers has oxygen added therein.
    Type: Grant
    Filed: July 10, 2013
    Date of Patent: November 11, 2014
    Assignee: Furukawa Electric Co., Ltd.
    Inventors: Takuya Kokawa, Tatsuyuki Shinagawa, Masayuki Iwami, Kazuyuki Umeno, Sadahiro Kato
  • Publication number: 20140084298
    Abstract: A nitride compound semiconductor device includes: a substrate; a buffer layer formed on the substrate and including a plurality of composite layers each layered of: a first layer formed of a nitride compound semiconductor; and a second layer formed of a nitride compound semiconductor containing aluminum and having a lattice constant smaller than a lattice constant of the first layer; a semiconductor operating layer formed on the buffer layer; and a plurality of electrodes formed on the semiconductor operating layer. At least one of the second layers has oxygen added therein.
    Type: Application
    Filed: July 10, 2013
    Publication date: March 27, 2014
    Inventors: Takuya KOKAWA, Tatsuyuki Shinagawa, Masayuki Iwami, Kazuyuki Umeno, Sadahiro Kato
  • Patent number: 8569800
    Abstract: A field effect transistor includes: a buffer layer that is formed on a substrate; a high resistance layer or a foundation layer that is formed on the buffer layer; a carbon-containing carrier concentration controlling layer that is formed on the high resistance layer or the foundation layer; a carrier traveling layer that is formed on the carrier concentration controlling layer; a carrier supplying layer that is formed on the carrier traveling layer; a recess that is formed from the carrier supplying layer up to a predetermined depth; source/drain electrodes that are formed on the carrier supplying layer with the recess intervening therebetween; a gate insulating film that is formed on the carrier supplying layer so as to cover the recess; and a gate electrode that is formed on the gate insulating film in the recess.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: October 29, 2013
    Assignee: Furukawa Electric Co., Ltd.
    Inventors: Nariaki Ikeda, Takuya Kokawa, Masayuki Iwami, Sadahiro Kato
  • Patent number: 8450782
    Abstract: A field effect transistor includes a high resistance layer on a substrate, a semiconductor operation layer that is formed on the high resistance layer and includes a channel layer that has the carbon concentration of not more than 1×1018 cm?3 and has the layer thickness of more than 10 nm and not more than 100 nm, a recess that is formed up to the inside of the channel layer in the semiconductor operation layer, source and drain electrodes that are formed on the semiconductor operation layer with the recess intervening therebetween, a gate insulating film that is formed on the semiconductor operation layer so as to cover the recess, and a gate electrode that is formed on the gate insulating film in the recess.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: May 28, 2013
    Assignee: Furukawa Electric Co., Ltd.
    Inventors: Yoshihiro Sato, Takehiko Nomura, Nariaki Ikeda, Takuya Kokawa, Masayuki Iwami, Sadahiro Kato
  • Patent number: 8421182
    Abstract: A semiconductor layer of a second conductive type is formed on a RESURF layer of a first conductive type that is formed on a buffer layer. A contact layer of the first conductive type is formed in or on the semiconductor layer. A source electrode is formed on the contact layer. A drain electrode is formed on the RESURF layer. A gate insulating film is formed on the semiconductor layer to overlap with an end of the semiconductor layer. A gate electrode is formed on the gate insulating film to overlap with the end of the semiconductor layer. A channel formed near the end of the semiconductor layer is electrically connected to the RESURF layer.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: April 16, 2013
    Assignee: Furukawa Electric Co., Ltd.
    Inventors: Takehiko Nomura, Seikoh Yoshida, Sadahiro Kato
  • Patent number: 8338859
    Abstract: A semiconductor electronic device comprises a substrate; a buffer layer formed on said substrate, having two or more layers of composite layers in which a first semiconductor layer comprising nitride based compound semiconductor having smaller lattice constant and greater coefficient of thermal expansion than the substrate and a second semiconductor layer comprising nitride based compound semiconductor having smaller lattice constant and smaller coefficient of thermal expansion than the first semiconductor layer are alternately laminated; a semiconductor operating layer comprising nitride based compound semiconductor formed on said buffer layer; a dislocation reducing layer comprising nitride based compound semiconductor, formed in a location between a location directly under said buffer layer and inner area of said semiconductor operating layer, and comprising a lower layer area and an upper layer area each having an uneven boundary surface, wherein threading dislocation extending from the lower layer area t
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: December 25, 2012
    Assignee: Furukawa Electric Co., Ltd
    Inventors: Takuya Kokawa, Sadahiro Kato, Yoshihiro Sato, Masayuki Iwami
  • Patent number: 8309988
    Abstract: Provided is a GaN based field effect transistor that is capable of normally-off operation, high breakdown voltage and large current. A body electrode 8 is provided on the bottom surface or the top surface of the field effect transistor. When the body electrode 8 is provided on the bottom surface, a p-type GaN layer 4 is provided on a p-type Si substrate 2 via a buffer layer 3 comprising a plurality of AlN layers 31 and GaN layers 32, with the top layer of that buffer layer 3 being a thin AlN layer 31, and the body electrode 8 being formed on the bottom surface of the p-type Si substrate. When the body electrode 8 is provided on the top surface, a p-type GaN layer 4 is provided on a sapphire substrate 21 and an AlGaN layer 13 is provided on the area under the source electrode 5 and drain electrode 6, with the body electrode 8 being provided on top of the AlGaN layer 13. Holes 20 that are generated by an avalanche phenomenon run through the body electrode 8.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: November 13, 2012
    Assignee: Furukawa Electric Co., Ltd
    Inventors: Yuki Niiyama, Takehiko Nomura, Sadahiro Kato
  • Patent number: 8304809
    Abstract: In a GaN-based semiconductor device, an active layer of a GaN-based semiconductor is formed on a silicon substrate. A trench is formed in the active layer and extends from a top surface of the active layer to a depth reaching the silicon substrate. A first electrode is formed on an internal wall surface of the trench and extends from the top surface of the active layer to the silicon substrate. A second electrode is formed on the active layer to define a current path between the first electrode and the second electrode via the active layer in an on-state of the device. A bottom electrode is formed on a bottom surface of the silicon substrate and defines a bonding pad for the first electrode. The first electrode is formed of metal in direct ohmic contact with both the silicon substrate and the active layer.
    Type: Grant
    Filed: November 13, 2008
    Date of Patent: November 6, 2012
    Assignee: Furukawa Electric Co., Ltd.
    Inventors: Shusuke Kaya, Seikoh Yoshida, Masatoshi Ikeda, legal representative, Sadahiro Kato, Takehiko Nomura, Nariaki Ikeda, Masayuki Iwami, Yoshihiro Sato, Hiroshi Kambayashi, Koh Li
  • Patent number: 8134181
    Abstract: A semiconductor device includes a substrate; a buffer layer; and a compound semiconductor layer laminated on the substrate with the buffer layer in between. The buffer layer has a dislocation density in a plane in parallel to an in-plane direction thereof, so that a volume resistivity of the buffer layer becomes a substantially maximum value.
    Type: Grant
    Filed: August 12, 2009
    Date of Patent: March 13, 2012
    Assignee: Furukawa Electric Co., Ltd.
    Inventors: Yoshihiro Sato, Sadahiro Kato, Seikoh Yoshida
  • Patent number: 8067787
    Abstract: A semiconductor electronic device comprises a substrate; a buffer layer formed on the substrate, the buffer layer including not less than two layers of composite layer in which a first semiconductor layer formed of a nitride-based compound semiconductor layer having a lattice constant smaller than a lattice constant of the substrate and a thermal expansion coefficient larger than a thermal expansion coefficient of the substrate and a second semiconductor layer formed of a nitride-based compound semiconductor having a lattice constant smaller than a lattice constant of the first semiconductor layer and a thermal expansion coefficient larger than a thermal expansion coefficient of the substrate are alternately laminated; an intermediate layer provided between the substrate and the buffer layer, the intermediate layer being formed of a nitride-based compound semiconductor having a lattice constant smaller than a lattice constant of the first semiconductor layer and a thermal expansion coefficient larger than a t
    Type: Grant
    Filed: February 3, 2009
    Date of Patent: November 29, 2011
    Assignee: The Furukawa Electric Co., Ltd
    Inventors: Takuya Kokawa, Sadahiro Kato, Yoshihiro Sato, Masayuki Iwami
  • Publication number: 20110241017
    Abstract: A field effect transistor includes: a buffer layer that is formed on a substrate; a high resistance layer or a foundation layer that is formed on the buffer layer; a carbon-containing carrier concentration controlling layer that is formed on the high resistance layer or the foundation layer; a carrier traveling layer that is formed on the carrier concentration controlling layer; a carrier supplying layer that is formed on the carrier traveling layer; a recess that is formed from the carrier supplying layer up to a predetermined depth; source/drain electrodes that are formed on the carrier supplying layer with the recess intervening therebetween; a gate insulating film that is formed on the carrier supplying layer so as to cover the recess; and a gate electrode that is formed on the gate insulating film in the recess
    Type: Application
    Filed: March 31, 2011
    Publication date: October 6, 2011
    Applicant: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Nariaki IKEDA, Takuya KOKAWA, Masayuki IWAMI, Sadahiro KATO
  • Publication number: 20110241088
    Abstract: A field effect transistor includes a high resistance layer on a substrate, a semiconductor operation layer that is formed on the high resistance layer and includes a channel layer that has the carbon concentration of not more than 1×1018 cm?3 and has the layer thickness of more than 10 nm and not more than 100 nm, a recess that is formed up to the inside of the channel layer in the semiconductor operation layer, source and drain electrodes that are formed on the semiconductor operation layer with the recess intervening therebetween, a gate insulating film that is formed on the semiconductor operation layer so as to cover the recess, and a gate electrode that is formed on the gate insulating film in the recess.
    Type: Application
    Filed: March 30, 2011
    Publication date: October 6, 2011
    Applicant: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Yoshihiro SATO, Takehiko NOMURA, Nariaki IKEDA, Takuya KOKAWA, Masayuki IWAMI, Sadahiro KATO
  • Patent number: 7943496
    Abstract: A method of manufacturing a GaN-based field effect transistor is provided by which a lower resistance and a higher breakdown voltage are obtained and which is less affected by a current collapse.
    Type: Grant
    Filed: February 17, 2010
    Date of Patent: May 17, 2011
    Assignee: Furukawa Electric Co., Ltd.
    Inventors: Takehiko Nomura, Nariaki Ikeda, Shusuke Kaya, Sadahiro Kato
  • Patent number: 7812371
    Abstract: The field effect transistor includes a laminated structure in which a buffer layer, and an electron transporting layer (undoped GaN layer), and an electron supplying layer (undoped AlGaN layer) are laminated in sequence on a sapphire substrate. An npn laminated structure is formed on a source region of the electron supplying layer, and a source electrode is formed on the npn laminated structure. A drain electrode is formed in a drain region of the electron supplying layer, and an insulating film is formed in an opening region formed in the gate region. When a forward voltage greater than a threshold is applied to the gate electrode, an inversion layer is formed and the drain current flows. By changing a thickness and an impurity concentration of the p-type GaN layer, the threshold voltage can be controlled. The electrical field concentration between the gate electrode and the drain electrode is relaxed due to the drift layer, and voltage resistance improves.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: October 12, 2010
    Assignee: Furukawa Electric Co., Ltd.
    Inventors: Shusuke Kaya, Seikoh Yoshida, Masatoshi Ikeda, legal representative, Sadahiro Kato, Takehiko Nomura, Nariaki Ikeda, Masayuki Iwami, Yoshihiro Sato, Hiroshi Kambayashi, Yuki Niiyama
  • Publication number: 20100244097
    Abstract: Provided is a GaN based field effect transistor that is capable of normally-off operation, high breakdown voltage and large current. A body electrode 8 is provided on the bottom surface or the top surface of the field effect transistor. When the body electrode 8 is provided on the bottom surface, a p-type GaN layer 4 is provided on a p-type Si substrate 2 via a buffer layer 3 comprising a plurality of AlN layers 31 and GaN layers 32, with the top layer of that buffer layer 3 being a thin AlN layer 31, and the body electrode 8 being formed on the bottom surface of the p-type Si substrate. When the body electrode 8 is provided on the top surface, a p-type GaN layer 4 is provided on a sapphire substrate 21 and an AlGaN layer 13 is provided on the area under the source electrode 5 and drain electrode 6, with the body electrode 8 being provided on top of the AlGaN layer 13. Holes 20 that are generated by an avalanche phenomenon run through the body electrode 8.
    Type: Application
    Filed: March 26, 2010
    Publication date: September 30, 2010
    Applicant: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Yuki Niiyama, Takehiko Nomura, Sadahiro Kato