Patents by Inventor Sadahiro Kishii
Sadahiro Kishii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8791561Abstract: A support substrate includes a first surface and a second surface located above the level of the first surface. Chips are mounted on the first surface. A first insulating film is disposed over each chip. First conductive plugs are connected to the chip extending through each first insulating film. Filler material made of resin filling a space between chips. Wirings are disposed over the first insulating film and the filler material for interconnecting different chips. The second surface, an upper surface of the first insulating film and an upper surface of the filler material are located at the same level.Type: GrantFiled: February 11, 2013Date of Patent: July 29, 2014Assignees: Fujitsu Limited, Shinko Electric Industries Co., Ltd.Inventors: Sadahiro Kishii, Tsuyoshi Kanki, Yoshihiro Nakata, Yasushi Kobayashi, Masato Tanaka, Akio Rokugawa
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Patent number: 8702826Abstract: A method for producing abrasive agents includes: adding a silica to a manganese compound; heat-treating the manganese compound to which the silica has been added; forming abrasive grains by milling the manganese compound to which the silica has been added and which has been heat-treated; and adding a solvent to the abrasive grains.Type: GrantFiled: April 4, 2013Date of Patent: April 22, 2014Assignee: Fujitsu LimitedInventor: Sadahiro Kishii
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Publication number: 20130333298Abstract: A method for producing abrasive agents includes: adding a silica to a manganese compound; heat-treating the manganese compound to which the silica has been added; forming abrasive grains by milling the manganese compound to which the silica has been added and which has been heat-treated; and adding a solvent to the abrasive grains.Type: ApplicationFiled: April 4, 2013Publication date: December 19, 2013Applicant: FUJITSU LIMITEDInventor: Sadahiro KISHII
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Patent number: 8399295Abstract: A support substrate includes a first surface and a second surface located above the level of the first surface. Chips are mounted on the first surface. A first insulating film is disposed over each chip. First conductive plugs are connected to the chip extending through each first insulating film. Filler material made of resin filling a space between chips. Wirings are disposed over the first insulating film and the filler material for interconnecting different chips. The second surface, an upper surface of the first insulating film and an upper surface of the filler material are located at the same level.Type: GrantFiled: February 2, 2011Date of Patent: March 19, 2013Assignees: Fujitsu Limited, Shinko Electric Industries Co., Ltd.Inventors: Sadahiro Kishii, Tsuyoshi Kanki, Yoshihiro Nakata, Yasushi Kobayashi, Masato Tanaka, Akio Rokugawa
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Patent number: 8067791Abstract: A semiconductor device formed by the steps of: forming a dummy electrode 22n and a dummy electrode 22p; forming a metal film 32 on the dummy electrode 22p; conducting a thermal treatment at a first temperature to substitute the dummy electrode 22n with an electrode 34a of a material containing the constituent material of the metal film 32; forming a metal film 36 on the dummy electrode 22n; and conducting a thermal treatment at a second temperature, which is lower than the first temperature and at which an interdiffusion of constituent materials between the electrode 34a and the metal film 36 does not take place, to substitute the second dummy electrode with an electrode 34b of a material containing the constituent material of the metal film 36.Type: GrantFiled: November 18, 2009Date of Patent: November 29, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Hiroshi Kudo, Junko Naganuma, Sadahiro Kishii
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Publication number: 20110187002Abstract: A support substrate includes a first surface and a second surface located above the level of the first surface. Chips are mounted on the first surface. A first insulating film is disposed over each chip. First conductive plugs are connected to the chip extending through each first insulating film. Filler material made of resin filling a space between chips. Wirings are disposed over the first insulating film and the filler material for interconnecting different chips. The second surface, an upper surface of the first insulating film and an upper surface of the filler material are located at the same level.Type: ApplicationFiled: February 2, 2011Publication date: August 4, 2011Applicants: FUJITSU LIMITED, SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Sadahiro Kishii, Tsuyoshi Kanki, Yoshihiro Nakata, Yasushi Kobayashi, Masato Tanaka, Akio Rokugawa
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Patent number: 7951686Abstract: A trench is formed in a surface layer of a semiconductor substrate, the trench surrounding an active region. A lower insulating film made of insulating material is deposited over the semiconductor device, the lower insulating film filling a lower region of the trench and leaving an empty space in an upper region. An upper insulating film made of insulating material having therein a tensile stress is deposited on the lower insulating film, the upper insulating film filling the empty space left in the upper space. The upper insulating film and the lower insulating film deposited over the semiconductor substrate other than in the trench are removed.Type: GrantFiled: February 18, 2010Date of Patent: May 31, 2011Assignee: Fujitsu LimitedInventors: Sadahiro Kishii, Hirofumi Watatani, Masanori Terahara, Ryo Tanabe, Kaina Suzuki, Shigeo Satoh
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Publication number: 20100144117Abstract: A trench is formed in a surface layer of a semiconductor substrate, the trench surrounding an active region. A lower insulating film made of insulating material is deposited over the semiconductor device, the lower insulating film filling a lower region of the trench and leaving an empty space in an upper region. An upper insulating film made of insulating material having therein a tensile stress is deposited on the lower insulating film, the upper insulating film filling the empty space left in the upper space. The upper insulating film and the lower insulating film deposited over the semiconductor substrate other than in the trench are removed.Type: ApplicationFiled: February 18, 2010Publication date: June 10, 2010Applicant: FUJITSU LIMITEDInventors: Sadahiro Kishii, Hirofumi Watatani, Masanori Terahara, Ryo Tanabe, Kaina Suzuki, Shigeo Satoh
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Patent number: 7701016Abstract: A trench is formed in the surface layer of a semiconductor substrate, surrounding an active region. A lower insulating film made of insulating material fills a lower region of the trench. An upper insulating film fills a region of the trench above the lower insulating film. The upper insulating film has therein a stress generating tensile strain in a surface layer of the active region.Type: GrantFiled: October 3, 2006Date of Patent: April 20, 2010Assignee: Fujitsu LimitedInventors: Sadahiro Kishii, Hirofumi Watatani, Masanori Terahara, Ryo Tanabe, Kaina Suzuki, Shigeo Satoh
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Publication number: 20100059828Abstract: A semiconductor device formed by the steps of: forming a dummy electrode 22n and a dummy electrode 22p; forming a metal film 32 on the dummy electrode 22p; conducting a thermal treatment at a first temperature to substitute the dummy electrode 22n with an electrode 34a of a material containing the constituent material of the metal film 32; forming a metal film 36 on the dummy electrode 22n; and conducting a thermal treatment at a second temperature, which is lower than the first temperature and at which an interdiffusion of constituent materials between the electrode 34a and the metal film 36 does not take place, to substitute the second dummy electrode with an electrode 34b of a material containing the constituent material of the metal film 36.Type: ApplicationFiled: November 18, 2009Publication date: March 11, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Hiroshi KUDO, Junko NAGANUMA, Sadahiro KISHII
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Patent number: 7642577Abstract: The method for fabricating a semiconductor device comprises the steps of: forming a dummy electrode 22n and a dummy electrode 22p; forming a metal film 32 on the dummy electrode 22p; conducting a thermal treatment at a first temperature to substitute the dummy electrode 22n with an electrode 34a of a material containing the constituent material of the metal film 32; forming a metal film 36 on the dummy electrode 22n; and conducting a thermal treatment at a second temperature, which is lower than the first temperature and at which an interdiffusion of constituent materials between the electrode 34a and the metal film 36 does not take place, to substitute the second dummy electrode with an electrode 34b of a material containing the constituent material of the metal film 36.Type: GrantFiled: October 7, 2005Date of Patent: January 5, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Hiroshi Kudo, Junko Naganuma, Sadahiro Kishii
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Patent number: 7637270Abstract: An abrasive includes abrasive grains, a solvent, and an additive. MnO2, Mn2O3, Mn3O4, MnO or a mixture thereof as the abrasive grains, H2O2 as the solvent, and HNO3, an organic acid, H2O2, etc., as the additive are employed. The abrasive is solidified with cooling, etc. The abrasive and the additive can be supplied to a polishing apparatus through separate routes.Type: GrantFiled: June 26, 2006Date of Patent: December 29, 2009Assignee: Fujitsu LimitedInventor: Sadahiro Kishii
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Patent number: 7501686Abstract: A semiconductor device is disclosed that includes a semiconductor substrate, a device region disposed at a predetermined location of the semiconductor substrate, and a shallow trench isolation region that isolates the device region. The shallow trench isolation region includes a trench, a nitride film liner disposed at an upper portion of a side wall of the trench, and a thermal oxide film disposed at a lower portion of the side wall of the trench. The shallow trench isolation is arranged such that the width of a second portion of the shallow trench isolation region at which the thermal oxide film is disposed may be wider than the width of a first portion of the shallow trench isolation region at which the lower end of the nitride film liner is disposed.Type: GrantFiled: February 22, 2006Date of Patent: March 10, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Masaki Okuno, Sadahiro Kishii, Hiroshi Morioka, Masanori Terahara, Shigeo Satoh, Kaina Suzuki
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Publication number: 20070228488Abstract: A trench is formed in the surface layer of a semiconductor substrate, surrounding an active region. A lower insulating film made of insulating material fills a lower region of the trench. An upper insulating film fills a region of the trench above the lower insulating film. The upper insulating film has therein a stress generating tensile strain in a surface layer of the active region.Type: ApplicationFiled: October 3, 2006Publication date: October 4, 2007Applicant: FUJITSU LIMITEDInventors: Sadahiro Kishii, Hirofumi Watatani, Masanori Terahara, Ryo Tanabe, Kaina Suzuki, Shigeo Satoh
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Publication number: 20060281245Abstract: A semiconductor device is disclosed that includes a semiconductor substrate, a device region disposed at a predetermined location of the semiconductor substrate, and a shallow trench isolation region that isolates the device region. The shallow trench isolation region includes a trench, a nitride film liner disposed at an upper portion of a side wall of the trench, and a thermal oxide film disposed at a lower portion of the side wall of the trench. The shallow trench isolation is arranged such that the width of a second portion of the shallow trench isolation region at which the thermal oxide film is disposed may be wider than the width of a first portion of the shallow trench isolation region at which the lower end of the nitride film liner is disposed.Type: ApplicationFiled: February 22, 2006Publication date: December 14, 2006Applicant: FUJITSU LIMITEDInventors: Masaki Okuno, Sadahiro Kishii, Hiroshi Morioka, Masanori Terahara, Shigeo Satoh, Kaina Suzuki
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Publication number: 20060241006Abstract: An abrasive includes abrasive grains, a solvent, and an additive. MnO2, Mn2O3, Mn3O4, MnO or a mixture thereof as the abrasive grains, H2O2 as the solvent, and HNO3, an organic acid, H2O2, etc., as the additive are employed. The abrasive is solidified with cooling, etc. The abrasive and the additive can be supplied to a polishing apparatus through separate routes.Type: ApplicationFiled: June 26, 2006Publication date: October 26, 2006Applicant: FUJITSU LIMITEDInventor: Sadahiro Kishii
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Patent number: 7064038Abstract: The method for fabricating a semiconductor device comprises the steps of: forming a dummy electrode 22n and a dummy electrode 22p; forming a metal film 32 on the dummy electrode 22p; conducting a thermal treatment at a first temperature to substitute the dummy electrode 22n with an electrode 34a of a material containing the constituent material of the metal film 32; forming a metal film 36 on the dummy electrode 22n; and conducting a thermal treatment at a second temperature, which is lower than the first temperature and at which an interdiffusion of constituent materials between the electrode 34a and the metal film 36 does not take place, to substitute the second dummy electrode with an electrode 34b of a material containing the constituent material of the metal film 36.Type: GrantFiled: January 12, 2004Date of Patent: June 20, 2006Assignee: Fujitsu LimitedInventors: Hiroshi Kudo, Junko Naganuma, Sadahiro Kishii
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Publication number: 20060035427Abstract: The method for fabricating a semiconductor device comprises the steps of: forming a dummy electrode 22n and a dummy electrode 22p; forming a metal film 32 on the dummy electrode 22p; conducting a thermal treatment at a first temperature to substitute the dummy electrode 22n with an electrode 34a of a material containing the constituent material of the metal film 32; forming a metal film 36 on the dummy electrode 22n; and conducting a thermal treatment at a second temperature, which is lower than the first temperature and at which an interdiffusion of constituent materials between the electrode 34a and the metal film 36 does not take place, to substitute the second dummy electrode with an electrode 34b of a material containing the constituent material of the metal film 36.Type: ApplicationFiled: October 7, 2005Publication date: February 16, 2006Applicant: FUJITSU LIMITEDInventors: Hiroshi Kudo, Junko Naganuma, Sadahiro Kishii
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Publication number: 20040142546Abstract: The method for fabricating a semiconductor device comprises the steps of: forming a dummy electrode 22n and a dummy electrode 22p; forming a metal film 32 on the dummy electrode 22p; conducting a thermal treatment at a first temperature to substitute the dummy electrode 22n with an electrode 34a of a material containing the constituent material of the metal film 32; forming a metal film 36 on the dummy electrode 22n; and conducting a thermal treatment at a second temperature, which is lower than the first temperature and at which an interdiffusion of constituent materials between the electrode 34a and the metal film 36 does not take place, to substitute the second dummy electrode with an electrode 34b of a material containing the constituent material of the metal film 36.Type: ApplicationFiled: January 12, 2004Publication date: July 22, 2004Applicant: FUJITSU LIMITEDInventors: Hiroshi Kudo, Junko Naganuma, Sadahiro Kishii
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Publication number: 20030217518Abstract: An abrasive includes abrasive grains, a solvent, and an additive. MnO2, Mn2O3, Mn3O4, MnO or a mixture thereof as the abrasive grains, H2O2 as the solvent, and HNO3, an organic acid, H2O2, etc., as the additive are employed. The abrasive is solidified with cooling, etc. The abrasive and the additive can be supplied to a polishing apparatus through separate routes.Type: ApplicationFiled: May 19, 2003Publication date: November 27, 2003Applicant: FUJITSU LIMITEDInventor: Sadahiro Kishii