Abstract: A blocking layer is formed on a hard mask having an initial thickness. Lines are fabricated by patterning the blocking layer and the hard mask to provide a line segment, the line segment having a first dimension measured across the line segment; reacting a surface layer of the line segment to form a layer of a reaction product on a remaining portion of the line segment; and removing the reaction product without attacking the remaining portion of the line segment and without attacking the blocking layer and the substrate to form the line segment with a second dimension across the line segment that is smaller than the first dimension. The blocking layer prevents the formation of reaction product on the hard mask so that the initial thickness of the hard mask is maintained. The blocking layer can also serve as an ARC layer for photoresist patterning so that the use of an additional film layer is not required.

Abstract: A method for precise thinning to form a recess to a precise depth in a crystalline silicon layer, which can be used to form various devices, such as MOSFET devices, includes the following steps. Form a patterning mask with a window therethrough over the top surface of the silicon layer. Form an amorphized region in the top surface of the silicon layer below the window. Selectively etch away the amorphized region of the silicon layer to form a recess in the surface of the silicon layer, and remove the patterning mask In the case of an MOSFET device form a hard mask below the patterning mask with the window extending therethrough. Then create sidewall spacers in the window through the hard mask and form a gate electrode stack in the window. Then remove the hard mask and form the source/drain extensions, halos and regions plus silicide and complete the MOSFET device.

Abstract: A method for modulating the stress caused by bird beak formation of small width devices by a nitrogen plasma treatment. The nitrogen plasma process forms a nitride liner about the trench walls that serves to prevent the formation of bird beaks in the isolation region during a subsequent oxidation step. In one embodiment, the plasma nitridation process occurs after trench etching, but prior to trench fill. In yet another embodiment, the plasma nitridation process occurs after trench fill. In yet another embodiment, a block mask is formed over predetermined active areas of the etched substrate prior to the plasma nitridation process. This embodiment is used in protecting the PFET device area from the plasma nitridation process thereby providing a means to form a PFET device area in which stress caused by bird beak formation increases the device performance of the PFET.

Abstract: A method for modulating the stress caused by bird beak formation of small width devices by a nitrogen plasma treatment. The nitrogen plasma process forms a nitride liner about the trench walls that serves to prevent the formation of bird beaks in the isolation region during a subsequent oxidation step. In one embodiment, the plasma nitridation process occurs after trench etching, but prior to trench fill. In yet another embodiment, the plasma nitridation process occurs after trench fill. In yet another embodiment, a block mask is formed over predetermined active areas of the etched substrate prior to the plasma nitridation process. This embodiment is used in protecting the PFET device area from the plasma nitridation process thereby providing a means to form a PFET device area in which stress caused by bird beak formation increases the device performance of the PFET.

Abstract: A blocking layer is formed on a hard mask having an initial thickness. Lines are fabricated by patterning the blocking layer and the hard mask to provide a line segment, the line segment having a first dimension measured across the line segment; reacting a surface layer of the line segment to form a layer of a reaction product on a remaining portion of the line segment; and removing the reaction product without attacking the remaining portion of the line segment and without attacking the blocking layer and the substrate to form the line segment with a second dimension across the line segment that is smaller than the first dimension. The blocking layer prevents the formation of reaction product on the hard mask so that the initial thickness of the hard mask is maintained. The blocking layer can also serve as an ARC layer for photoresist patterning so that the use of an additional film layer is not required.

Abstract: The present invention provides a method for preserving an oxide hard mask for the purpose of avoiding growth of epi Si on the gate stack during raised source/drain formation. The oxide hard mask is preserved in the present invention by utilizing a method which includes a chemical oxide removal processing step instead of an aqueous HF etchant.

Abstract: The present invention provides a method for preserving an oxide hard mask for the purpose of avoiding growth of epi Si on the gate stack during raised source/drain formation. The oxide hard mask is preserved in the present invention by utilizing a method which includes a chemical oxide removal processing step instead of an aqueous HF etchant.

Abstract: A method for removing carbon from or stripping a TERA layer. The method includes exposing the TERA layer to a plasma containing an effective amount of nitrogen, and, optionally, oxygen or fluorine. The method is compatible with fluorine based etching systems, and may thus be performed in the same etching system as other etching steps. For example, the method may be performed in the same system as a fluorine based plasma etch for oxide or nitride. The invention includes the method of stripping a TERA layer, etching an oxide layer, and etching a nitride layer in situ in the same etching system. The method is performed at low ion energies to avoid damaging oxide or nitride layers under the TERA film and to provide good selectivity.

Abstract: A method of forming a structure having sub-lithographic dimensions is provided. The method includes: forming a chamfered mandrel on a substrate, the mandrel having an angled surface; and performing an angled ion implantation to obtain an implanted shadow region in the substrate, the implanted shadow mask having at least one sub-lithographic dimension.

Abstract: Divot fill methods of incorporating thin SiO2 spacer and/or annealing caps into a complementary metal oxide semiconductor (CMOS) processing flow are provided. In accordance with the present invention, the divot fill processes provide a means for protecting the exposed surfaces of the thin SiO2 spacer and/or annealing cap such that those surfaces are not capable of being attacked by a subsequent silicide pre-cleaning step. CMOS devices including thin SiO2 spacer and/or annealing caps whose surfaces are protected such that those surfaces are not capable of being attacked by a subsequent silicide pre-cleaning or other process steps are also provided.

Abstract: Divot fill methods of incorporating thin SiO2 spacer and/or annealing caps into a complementary metal oxide semiconductor (CMOS) processing flow are provided. In accordance with the present invention, the divot fill processes provide a means for protecting the exposed surfaces of the thin SiO2 spacer and/or annealing cap such that those surfaces are not capable of being attacked by a subsequent silicide pre-cleaning step. CMOS devices including thin SiO2 spacer and/or annealing caps whose surfaces are protected such that those surfaces are not capable of being attacked by a subsequent silicide pre-cleaning or other process steps are also provided.