Patents by Inventor Sadao Nakashima

Sadao Nakashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080268644
    Abstract: There are provided the steps of loading a substrate into a reaction vessel; forming a film on the substrate while supplying a film forming gas into the reaction vessel; unloading the substrate after film formation from the reaction vessel; supplying a cleaning gas into the reaction vessel while lowering a temperature in the reaction vessel and removing a deposit deposited on at least an inner wall of the reaction vessel in the film forming step.
    Type: Application
    Filed: February 5, 2008
    Publication date: October 30, 2008
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Kenji Kameda, Naonori Akae, Kenichi Suzaki, Yushin Takasawa, Sadao Nakashima
  • Publication number: 20070275570
    Abstract: A heat treatment device where intervals between substrates supported by a supporter is reduced so that the number of substrates to be treated can be increased. A heat treatment device has a reaction furnace for treating substrates and a supporter for supporting the substrates in plural stages in the reaction furnace. The supporter has supporting plates in contact with the substrates and supporting members for supporting the supporting plates. A supporting plate and a supporting member are superposed on each other at least a part in the thickness direction.
    Type: Application
    Filed: January 20, 2005
    Publication date: November 29, 2007
    Applicant: Hitachi Kokusai Electric Inc.
    Inventors: Naoto Nakamura, Iwao Nakamura, Tomoharu Shimada, Akira Morohashi, Keishin Yamazaki, Sadao Nakashima
  • Publication number: 20070194411
    Abstract: A thermal treatment apparatus, a method for manufacturing a semiconductor device, and a method for manufacturing a substrate, wherein the occurrence of slip dislocation in a substrate during heat treatment is reduced, and a high-quality semiconductor device can be manufactured, are intended to be provided. A substrate support 30 is formed from a main body portion 56 and a supporting portion 58. In the main body portion 56, a plurality of placing portions 66 extend parallel, and supporting portions 58 are provided on the placing portions 66. A substrate 68 is placed on the supporting portion 58. The supporting portion 58 has a smaller area than an area of a flat face of the substrate, and is formed from a silicon plate having a thickness larger than thickness of the substrate, so that deformation during heat treatment is reduced. The supporting portion 58 is made of silicon, and a layer coated with silicon carbide (SiC) is formed on a substrate-placing face of the supporting portion 58.
    Type: Application
    Filed: September 26, 2003
    Publication date: August 23, 2007
    Applicant: Hitachi Kokusai Electric Inc.
    Inventors: Naoto Nakamura, Iwao Nakamura, Tomoharu Shimada, Kenichi Ishiguro, Sadao Nakashima
  • Publication number: 20030170583
    Abstract: A heat treatment apparatus for performing a heat treatment on one or more substrates includes a substrate support device holding the substrates, the substrate support device having a main body and a contact portion being in contact with a substrate. A surface of the main body is made of a material different from that of the contact portion, and at least a surface of the contact portion is made of either glassy carbon or graphite.
    Type: Application
    Filed: February 27, 2003
    Publication date: September 11, 2003
    Applicant: Hitachi Kokusai Electric Inc.
    Inventors: Sadao Nakashima, Tomoharu Shimada, Kenichi Ishiguro
  • Patent number: 5989981
    Abstract: A method of manufacturing an SOI substrate uses an SOI substrate having a first single-crystal silicon layer, an insulating layer formed on the first single-crystal silicon layer, and a second single-crystal silicon layer formed on the insulating layer. The surface of the second single-crystal silicon layer is thermally oxidized. The second single-crystal silicon layer is controlled to have a predetermined thickness by removing the thermally oxidized surface. This step controlling the second single-crystal silicon layer to have a predetermined thickness includes the step of eliminating, by annealing, a stacking fault formed by the thermal oxidation.
    Type: Grant
    Filed: July 2, 1997
    Date of Patent: November 23, 1999
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Sadao Nakashima, Terukazu Ohno, Toshiaki Tsuchiya, Tetsushi Sakai, Shinji Nakamura, Takemi Ueki, Yuichi Kado, Tadao Takeda
  • Patent number: 5918136
    Abstract: A method of producing an SOI substrate having a single-crystal silicon layer on a buried oxide layer in an electrically insulating state from the substrate by implanting oxygen ions into a single crystal silicon substrate and practicing an anneal processing in an inert gas atmosphere at high temperatures to form the buried oxide layer. After the anneal processing in which the thickness of the buried oxide layer becomes a theoretical value in conformity with the thickness of the buried oxide layer formed by the implanted oxygen, the oxidation processing of the substrate is carried out in a high temperature oxygen atmosphere.
    Type: Grant
    Filed: August 19, 1997
    Date of Patent: June 29, 1999
    Assignees: Komatsu Electronic Metals Co., Ltd.,, Nippon Telegraph and Telephone Corporation, NTT Electronics Technology Corporation
    Inventors: Sadao Nakashima, Katsutoshi Izumi, Norihiko Ohwada, Tatsuhiko Katayama
  • Patent number: 5665613
    Abstract: A SIMOX substrate 1 is processed through high temperature oxidation treatment after forming a mask-pattern 3 to shield specified electrodes from oxidation in order to increase partly a thickness of a buffed oxide layer 2 to form an area 4. Next, after an oxide film is removed from the surface of the substrate and LOCOS separation is practiced, MOSFET is produced by fabricating a source S and a drain D on the area 4 or the buffed oxide layer 2. Since the buried oxide layer corresponding to electrodes parts influenced by disadvantages of parasitic capacitance are thickened, an operation speed of an inverter is not much decreased and since mean thickness of the buried oxide layer can be thinner, a decrease of a drain electric current by negative electrical resistance can be suppressed. Furthermore, since the thickness of the buffed oxide layer can be controlled in response to each device, plural devices having different breakdown voltages are formed together on the same substrate.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: September 9, 1997
    Assignees: Komatsu Electronic Metals Co., Ltd., Nippon Telegraph and Telephone Corporation, NIT Electronics Technology Corporation
    Inventors: Sadao Nakashima, Katsutoshi Izumi, Norihiko Ohwada, Tatsuhiko Katayama
  • Patent number: 5658809
    Abstract: A method of producing an SOI substrate having a single-crystal silicon layer on a buried oxide layer in an electrically insulating state from the substrate by implanting oxygen ions into a single crystal silicon substrate and practicing an anneal processing in an inert gas atmosphere at high temperatures to form the buried oxide layer. After the anneal processing in which the thickness of the buried oxide layer becomes a theoretical value in conformity with the thickness of the buried oxide layer formed by the implanted oxygen, the oxidation processing of the substrate is carried out in a high temperature oxygen atmosphere.
    Type: Grant
    Filed: March 13, 1995
    Date of Patent: August 19, 1997
    Assignees: Komatsu Electronic Metals Co., Ltd., Nippon Telegraph and Telephone Corporation, NTT Electronics Technology Corporation
    Inventors: Sadao Nakashima, Katsutoshi Izumi, Norihiko Ohwada, Tatsuhiko Katayama