Abstract: A high speed sense amp supplies current to a bit line connected to a memory cell transistor and also detects a potential of the bit line. The potential of the bit line varies according to a conductive state of the memory cell transistor. The sense amp includes a load element and a first transistor connected in series between a first potential and the bit line. A second transistor is connected between the first potential and the bit line. The bit line is input to an inverter that has its output terminal connected to a gate of the first transistor. A differential amp has a first input terminal connected to a reference potential and a second input terminal connected to a node between the load element and the first transistor. The output of the differential amp indicates a difference between the reference potential and the bit line potential.

Abstract: A semiconductor memory device having a reduced circuit area. The semiconductor memory device includes a memory cell array connected to an address decoder, a sense amplifier, a write amplifier, and a command decoder. A first serial/parallel converter is adjacent to the address decoder. A parallel/serial converter is adjacent to the sense amplifier. A second serial/parallel converter is adjacent to the write amplifier. A third serial/parallel converter is adjacent to the command decoder. The serial/parallel converters and the parallel/serial converter are each connected to an input/output circuit via a pair of wires.

Abstract: A semiconductor memory device having a reduced circuit area. The semiconductor memory device includes a memory cell array connected to an address decoder, a sense amplifier, a write amplifier, and a command decoder. A first serial/parallel converter is adjacent to the address decoder. A parallel/serial converter is adjacent to the sense amplifier. A second serial/parallel converter is adjacent to the write amplifier. A third serial/parallel converter is adjacent to the command decoder. The serial/parallel converters and the parallel/serial converter are each connected to an input/output circuit via a pair of wires.

Abstract: A write control circuit that generates a control signal to initiate a write operation for a semiconductor memory device, such as an EEPROM, compensates for fluctuations in the supply voltage. The write control circuit includes a control potential generator that produces a first control potential which is kept higher than the ground potential and a second control potential which is kept lower than the supply potential. A first transistor is connected to the supply potential and receives a write potential at its gate. A second transistor is connected between the first transistor and ground and receives the first control potential at its gate. A third transistor is connected to the supply potential and receives the second control potential at its gate. A fourth transistor is connected between the third transistor and ground and receives a potential from a first node between the first and second transistors at its gate. The control signal is generated at a second node between the third and fourth transistors.

Abstract: A non-volatile semiconductor memory device including a memory cell transistor, a bit line connected to the memory cell transistor, a current controlling element connected between the bit line and a first potential, a dummy cell transistor connected between the bit line and a second potential, and a decoder connected to the memory cell transistor and the dummy cell transistor. The memory cell transistor has an electrically isolated floating gate electrode which varies an on resistance that depends on an amount of charge stored on the floating gate electrode.

Abstract: An address transition detector (ATD) for a memory device detects a change in an address signal and in response, produces a timing signal. The timing signal is used to align the timing of operation of a memory cell and a sense amp with the timing of the change in the address signal. The ATD includes a detection circuit for detecting a change in the address signal and a transistor having its gate connected to an output of the detection circuit, its source connected to ground and its drain connected to a first input terminal of a logic gate. An output of the logic gate is connected to an inverter. The output of the inverter is connected to a node between the transistor and the first input terminal of the logic gate. The output of the logic gate is also connected to a pair of series connected delay circuits. The output of the second delay circuit is input to a second input terminal of the logic gate.

Abstract: A word line is connected to a control gate of memory cell transistor, and a bit line and a source line are connected to a drain and a source of the memory cell transistor, respectively. A write clock having a certain crest value is applied to the source line, and an earth potential or a power supply potential is applied to the bit line in response to a read clock having a phase which is opposite to that of the write clock. A row selection clock which synchronizes with the write clock and a crest value of which is de-escalated is applied to the word line.

Abstract: A semiconductor memory device is described that has an improved read characteristics. The semiconductor memory device includes a plurality of memory cells, a reference cell, a comparator located between the memory cells and the reference cell, and a discriminator coupled to the comparator. The comparator compares the actual signal equivalent to a value of a current flowing in each of the memory cells and reference signals equivalent to a value of a current flowing in the reference cell with each other to output a comparison result signal in each of data reading operation modes. The discriminator discriminates a value of data stored in each of the memory cells based on the comparison result signal. The discriminator includes a circuit shared for discrimination of a data value in each of the data reading operation modes.

Abstract: A nonvolatile semiconductor memory device includes a plurality of floating gate type memory cell transistors, connected in parallel between a bit line and a source line and a plurality of floating gate type reference transistors. The reference transistors are arranged in a matrix, defining rows and columns. The memory cell transistors are arranged as a column in the matrix, such that one of the memory cell transistors is associated with a row of the reference transistors. A plurality of reference bit lines are connected to a respective drain of each of the memory cell transistors in a respective column. Each reference bit line has a capacitance different than the other reference bit lines, which allows multi-state information stored in the memory cell transistors to be determined in accordance with a dropping speed of the potential of the bit lines and plurality of respective reference bit lines.

Abstract: A static semiconductor memory device includes a semiconductor substrate, first and second load transistors located along a first power line, and first and second drive transistors located along a second power line. The device further includes first and second select transistors, a first connection line, a second connection line, and a capacitor. The first connection line is commonly connected a gate of the first load transistor and a gate of the first drive transistor to drains of the second load transistor, the second drive transistor and the first select transistor. The second connection line is commonly connected a gate of the second load transistor and a gate of the second drive transistor to drains of the first load transistor, the first drive transistor and the second select transistor. The capacitor is supplemented with at least one of the first connection line and the second connection line.

Abstract: A ruthenium-phosphine complex represented by the formula (I)Ru.sub.x H.sub.y Cl.sub.z (R--BINAP).sub.2 (S).sub.p (I)wherein R--BINAP represents tertiary phosphine represented by the formula (II) ##STR1## R which is the same represents hydrogen, methyl or t-butyl, S represents tertiary amine, y represents 0 or 1, and when y is 0, x represents 2, z represents 4 and p represents 1, and when y is 1, x represents 1, z represents 1 and p represents 0.

Abstract: Process for preparing omega-hydroxy fatty acids of the formulaROCH.sub.2 (CH.sub.2).sub.n CH.sub.2 CH.sub.2 CH.sub.2 COOHwherein R is H or acyl, and n is an integer of 0 to 18,by a very simple operation without a trouble of pollution, which comprises catalytically reacting an omega-hydroxy (or acyloxy)-alkyl-.gamma.-butyrolactone of the formula ##STR1## wherein R and n are as defined above, in the presence of a hydrogenolysis catalyst. Compounds of formula (2) are novel, and a process for preparing them is also provided.The subject compounds are particularly useful as intermediates in the production of macrocyclic musk perfumes.

Abstract: Process for preparing omega-hydroxy fatty acids of the formulaROCH.sub.2 (CH.sub.2).sub.n CH.sub.2 CH.sub.2 CH.sub.2 COOHwhereinR is H or acyl, and n is an integer of 0 to 18,by a very simple operation without a trouble of pollution, which comprises catalytically reacting an omega-hydroxy (or acyloxy)-alkyl-.gamma.-butyrolactone of the formula ##STR1## wherein R and n are as defined above, in the presence of a hydrogenolysis catalyst.Compounds of formula (2) are novel, and a process for preparing them is also provided.