Patents by Inventor Sadasivan Shankar
Sadasivan Shankar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11757026Abstract: Nanowire structures having wrap-around contacts are described. For example, a nanowire semiconductor device includes a nanowire disposed above a substrate. A channel region is disposed in the nanowire. The channel region has a length and a perimeter orthogonal to the length. A gate electrode stack surrounds the entire perimeter of the channel region. A pair of source and drain regions is disposed in the nanowire, on either side of the channel region. Each of the source and drain regions has a perimeter orthogonal to the length of the channel region. A first contact completely surrounds the perimeter of the source region. A second contact completely surrounds the perimeter of the drain region.Type: GrantFiled: October 16, 2020Date of Patent: September 12, 2023Assignee: Google LLCInventors: Stephen M. Cea, Cory E. Weber, Patrick H. Keys, Seiyon Kim, Michael G. Haverty, Sadasivan Shankar
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Publication number: 20210036137Abstract: Nanowire structures having wrap-around contacts are described. For example, a nanowire semiconductor device includes a nanowire disposed above a substrate. A channel region is disposed in the nanowire. The channel region has a length and a perimeter orthogonal to the length. A gate electrode stack surrounds the entire perimeter of the channel region. A pair of source and drain regions is disposed in the nanowire, on either side of the channel region. Each of the source and drain regions has a perimeter orthogonal to the length of the channel region. A first contact completely surrounds the perimeter of the source region. A second contact completely surrounds the perimeter of the drain region.Type: ApplicationFiled: October 16, 2020Publication date: February 4, 2021Inventors: Stephen M. CEA, Cory E. WEBER, Patrick H. KEYS, Seiyon KIM, Michael G. HAVERTY, Sadasivan SHANKAR
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Patent number: 10840366Abstract: Nanowire structures having wrap-around contacts are described. For example, a nanowire semiconductor device includes a nanowire disposed above a substrate. A channel region is disposed in the nanowire. The channel region has a length and a perimeter orthogonal to the length. A gate electrode stack surrounds the entire perimeter of the channel region. A pair of source and drain regions is disposed in the nanowire, on either side of the channel region. Each of the source and drain regions has a perimeter orthogonal to the length of the channel region. A first contact completely surrounds the perimeter of the source region. A second contact completely surrounds the perimeter of the drain region.Type: GrantFiled: October 3, 2019Date of Patent: November 17, 2020Assignee: Intel CorporationInventors: Stephen M. Cea, Cory E. Weber, Patrick H. Keys, Seiyon Kim, Michael G. Haverty, Sadasivan Shankar
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Publication number: 20200035818Abstract: Nanowire structures having wrap-around contacts are described. For example, a nanowire semiconductor device includes a nanowire disposed above a substrate. A channel region is disposed in the nanowire. The channel region has a length and a perimeter orthogonal to the length. A gate electrode stack surrounds the entire perimeter of the channel region. A pair of source and drain regions is disposed in the nanowire, on either side of the channel region. Each of the source and drain regions has a perimeter orthogonal to the length of the channel region. A first contact completely surrounds the perimeter of the source region. A second contact completely surrounds the perimeter of the drain region.Type: ApplicationFiled: October 3, 2019Publication date: January 30, 2020Inventors: Stephen M. CEA, Cory E. WEBER, Patrick H. KEYS, Seiyon KIM, Michael G. HAVERTY, Sadasivan SHANKAR
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Patent number: 10483385Abstract: Nanowire structures having wrap-around contacts are described. For example, a nanowire semiconductor device includes a nanowire disposed above a substrate. A channel region is disposed in the nanowire. The channel region has a length and a perimeter orthogonal to the length. A gate electrode stack surrounds the entire perimeter of the channel region. A pair of source and drain regions is disposed in the nanowire, on either side of the channel region. Each of the source and drain regions has a perimeter orthogonal to the length of the channel region. A first contact completely surrounds the perimeter of the source region. A second contact completely surrounds the perimeter of the drain region.Type: GrantFiled: December 23, 2011Date of Patent: November 19, 2019Assignee: Intel CorporationInventors: Stephen M. Cea, Cory E. Weber, Patrick H. Keys, Seiyon Kim, Michael G. Haverty, Sadasivan Shankar
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Publication number: 20170162661Abstract: Techniques are disclosed for forming contacts in silicon semiconductor devices. In some embodiments, a transition layer forms a non-reactive interface with the silicon semiconductor contact surface. In some such cases, a conductive material provides the contacts and the material forming a non-reactive interface with the silicon surface. In other cases, a thin semiconducting or insulating layer provides the non-reactive interface with the silicon surface and is coupled to conductive material of the contacts. The techniques can be embodied, for instance, in planar or non-planar (e.g., double-gate and tri-gate FinFETs) transistor devices.Type: ApplicationFiled: February 17, 2017Publication date: June 8, 2017Applicant: INTEL CORPORATIONInventors: MICHAEL G. HAVERTY, SADASIVAN SHANKAR, TAHIR GHANI, SEONGJUN PARK
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Patent number: 9577057Abstract: Techniques are disclosed for forming contacts in silicon semiconductor devices. In some embodiments, a transition layer forms a non-reactive interface with the silicon semiconductor contact surface. In some such cases, a conductive material provides the contacts and the material forming a non-reactive interface with the silicon surface. In other cases, a thin semiconducting or insulating layer provides the non-reactive interface with the silicon surface and is coupled to conductive material of the contacts. The techniques can be embodied, for instance, in planar or non-planar (e.g., double-gate and tri-gate FinFETs) transistor devices.Type: GrantFiled: October 19, 2015Date of Patent: February 21, 2017Assignee: INTEL CORPORATIONInventors: Michael G. Haverty, Sadasivan Shankar, Tahir Ghani, Seongjun Park
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Publication number: 20160043191Abstract: Techniques are disclosed for forming contacts in silicon semiconductor devices. In some embodiments, a transition layer forms a non-reactive interface with the silicon semiconductor contact surface. In some such cases, a conductive material provides the contacts and the material forming a non-reactive interface with the silicon surface. In other cases, a thin semiconducting or insulating layer provides the non-reactive interface with the silicon surface and is coupled to conductive material of the contacts. The techniques can be embodied, for instance, in planar or non-planar (e.g., double-gate and tri-gate FinFETs) transistor devices.Type: ApplicationFiled: October 19, 2015Publication date: February 11, 2016Applicant: INTEL CORPORATIONInventors: MICHAEL G. HAVERTY, SADASIVAN SHANKAR, TAHIR GHANI, SEONGJUN PARK
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Patent number: 9166004Abstract: Techniques are disclosed for forming contacts in silicon semiconductor devices. In some embodiments, a transition layer forms a non-reactive interface with the silicon semiconductor contact surface. In some such cases, a conductive material provides the contacts and the material forming a non-reactive interface with the silicon surface. In other cases, a thin semiconducting or insulating layer provides the non-reactive interface with the silicon surface and is coupled to conductive material of the contacts. The techniques can be embodied, for instance, in planar or non-planar (e.g., double-gate and tri-gate FinFETs) transistor devices.Type: GrantFiled: December 23, 2010Date of Patent: October 20, 2015Assignee: INTEL CORPORATIONInventors: Michael G. Haverty, Sadasivan Shankar, Tahir Ghani
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Publication number: 20150187900Abstract: An integrated circuit including a transistor, wherein the transistor includes a substrate including a surface, a gate oxide deposited on the substrate surface and a gate deposited on the gate oxide. The gate oxide includes one or more dielectric domains and a band gap matrix. The dielectric domains includes a first material and the band gap matrix includes a second material, wherein a dielectric constant of the first material is greater than a dielectric constant of the second material and a band gap of the first material is less than a band gap of the second material.Type: ApplicationFiled: December 26, 2013Publication date: July 2, 2015Inventors: Sadasivan Shankar, MARK BOHR, Michael Haverty
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Publication number: 20140209855Abstract: Nanowire structures having wrap-around contacts are described. For example, a nanowire semiconductor device includes a nanowire disposed above a substrate. A channel region is disposed in the nanowire. The channel region has a length and a perimeter orthogonal to the length. A gate electrode stack surrounds the entire perimeter of the channel region. A pair of source and drain regions is disposed in the nanowire, on either side of the channel region. Each of the source and drain regions has a perimeter orthogonal to the length of the channel region. A first contact completely surrounds the perimeter of the source region. A second contact completely surrounds the perimeter of the drain region.Type: ApplicationFiled: December 23, 2011Publication date: July 31, 2014Inventors: Stephen M. Cea, Cory E. Weber, Patrick H. Keys, Seiyon Kim, Michael G. Haverty, Sadasivan Shankar
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Patent number: 8779589Abstract: Electrical interconnects for integrated circuits and methods of fabrication of interconnects are provided. Devices are provided comprising copper interconnects having metallic liner layers comprising silver and a second component, such as, lanthanum, titanium, tungsten, zirconium, antimony, or calcium. Methods include providing a substrate having a trench or via formed therein, forming a silver alloy layer, comprising silver and a second component selected from the group consisting of lanthanum, titanium, tungsten, zirconium, antimony, and calcium, onto surfaces of the feature, depositing a copper seed layer, and depositing copper into the feature.Type: GrantFiled: December 20, 2010Date of Patent: July 15, 2014Assignee: Intel CorporationInventors: Harsono S. Simka, Daniel J. Zierath, Michael G. Haverty, Sadasivan Shankar
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Patent number: 8633534Abstract: An apparatus comprises a substrate, a phonon-decoupling layer formed on the substrate, a gate dielectric layer formed on the phonon-decoupling layer, a gate electrode formed on the gate dielectric layer, a pair of spacers formed on opposite sides of the gate electrode, a source region formed in the substrate subjacent to the phonon-decoupling layer, and a drain region formed in the substrate subjacent to the phonon-decoupling layer. The phonon-decoupling layer prevents the formation of a silicon dioxide interfacial layer and reduces coupling between high-k phonons and the field in the substrate.Type: GrantFiled: December 22, 2010Date of Patent: January 21, 2014Assignee: Intel CorporationInventors: Michael G. Haverty, Sadasivan Shankar
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Publication number: 20120161251Abstract: An apparatus comprises a substrate, a phonon-decoupling layer formed on the substrate, a gate dielectric layer formed on the phonon-decoupling layer, a gate electrode formed on the gate dielectric layer, a pair of spacers formed on opposite sides of the gate electrode, a source region formed in the substrate subjacent to the phonon-decoupling layer, and a drain region formed in the substrate subjacent to the phonon-decoupling layer. The phonon-decoupling layer prevents the formation of a silicon dioxide interfacial layer and reduces coupling between high-k phonons and the field in the substrate.Type: ApplicationFiled: December 22, 2010Publication date: June 28, 2012Inventors: Michael G. Haverty, Sadasivan Shankar
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Publication number: 20120161321Abstract: Techniques are disclosed for forming contacts in silicon semiconductor devices. In some embodiments, a transition layer forms a non-reactive interface with the silicon semiconductor contact surface. In some such cases, a conductive material provides the contacts and the material forming a non-reactive interface with the silicon surface. In other cases, a thin semiconducting or insulting layer provides the non-reactive interface with the silicon surface and is coupled to conductive material of the contacts. The techniques can be embodied, for instance, in planar or non-planar (e.g., double-gate and tri-gate FinFETs) transistor devices.Type: ApplicationFiled: December 23, 2010Publication date: June 28, 2012Inventors: Michael G. Haverty, Sadasivan Shankar, Tahir Ghani, Seongjun Park
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Publication number: 20120153478Abstract: Electrical interconnects for integrated circuits and methods of fabrication of interconnects are provided. Devices are provided comprising copper interconnects having metallic liner layers comprising silver and a second component, such as, lanthanum, titanium, tungsten, zirconium, antimony, or calcium. Methods include providing a substrate having a trench or via formed therein, forming a silver alloy layer, comprising silver and a second component selected from the group consisting of lanthanum, titanium, tungsten, zirconium, antimony, and calcium, onto surfaces of the feature, depositing a copper seed layer, and depositing copper into the feature.Type: ApplicationFiled: December 20, 2010Publication date: June 21, 2012Inventors: Harsono S. Simka, Daniel J. Zierath, Michael G. Haverty, Sadasivan Shankar
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Patent number: 8154121Abstract: Polymer interlayer dielectric and passivation materials for a microelectronic device are generally described. In one example, an apparatus includes one or more interconnect structures of a microelectronic device and one or more polymeric dielectric layers coupled with the one or more interconnect structures, the polymeric dielectric layers including copolymer backbones having a first monomeric unit and a second monomeric unit wherein the first monomeric unit has a different chemical structure than the second monomeric unit and wherein the copolymer backbones are cross-linked by a first cross-linker or a second cross-linker, or combinations thereof.Type: GrantFiled: February 26, 2008Date of Patent: April 10, 2012Assignee: Intel CorporationInventors: Kunal Shah, Michael Haverty, Sadasivan Shankar, Doug Ingerly, Grant Kloster
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Publication number: 20090212421Abstract: Polymer interlayer dielectric and passivation materials for a microelectronic device are generally described. In one example, an apparatus includes one or more interconnect structures of a microelectronic device and one or more polymeric dielectric layers coupled with the one or more interconnect structures, the polymeric dielectric layers including copolymer backbones having a first monomeric unit and a second monomeric unit wherein the first monomeric unit has a different chemical structure than the second monomeric unit and wherein the copolymer backbones are cross-linked by a first cross-linker or a second cross-linker, or combinations thereof.Type: ApplicationFiled: February 26, 2008Publication date: August 27, 2009Inventors: Kunal Shah, Michael Haverty, Sadasivan Shankar, Doug Ingerly, Grant Kloster
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Publication number: 20090166867Abstract: Cu interconnect structures using a bottomless liner to reduce the copper interfacial electron scattering and lower the electrical resistance are described in this application. The interconnect structures comprise a nucleation layer and a liner layer that may be formed by an oxide or nitride. The bottom portion of the liner layer is removed to expose the nucleation layer. Since the liner is bottomless, the nucleation layer is exposed during Cu deposition and serves to catalyze copper nucleation and enable selective growth of copper near the bottom (where the nucleation layer is exposed), rather than near the liner sidewalls. Thus, copper may be selectively grown with a bottom-up fill behavior than can reduce or eliminate formation of voids. Other embodiments are described.Type: ApplicationFiled: December 31, 2007Publication date: July 2, 2009Inventors: Harsono Simka, Sadasivan Shankar, Michael Haverty, Ramanan Chebiam, Florian Gstrein
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Publication number: 20090001591Abstract: Techniques for reducing resistivity in metal interconnects by compressive straining are generally described. In one example, an apparatus includes a dielectric substrate, a thin film of metal coupled with the dielectric substrate, and an interconnect metal coupled to the thin film of metal, the thin film of metal having a lattice parameter that is smaller than the lattice parameter of the interconnect metal to compressively strain the interconnect metal.Type: ApplicationFiled: June 29, 2007Publication date: January 1, 2009Inventors: Michael Haverty, Sadasivan Shankar, Kevin O'Brien, Seongjun Park