Abstract: Techniques for reducing resistivity in metal interconnects using interface control are generally described. In one example, an apparatus includes a dielectric substrate, a barrier film coupled with the dielectric substrate, a liner film of a selected material coupled with the barrier film, and a metal coupled with the liner film defining an interface region between the metal and the liner film, the material of the liner film being selected to provide an interface density of state about equal to or less than ten times the density of state of the metal in bulk form.

Abstract: A porous diamond dielectric material having a low dielectric constant and a method of forming such a material are described herein. A porous diamond dielectric material demonstrates high mechanical strength and has a low dielectric constant because of the presence of the pores. The dielectric constant is further decreased by the conversion of the sp2 type carbon bond terminations of the interior surface of the pores to sp3 type carbon bond terminations. This is accomplished by hydrogenation of the porous diamond dielectric material.

Abstract: A method for an electroplating cell which includes providing an anode chamber with at least two concentric anodes including an inner anode and an outer anode; generating a computer generated model with a simulation computer program; and selecting at least one current ratio from the computer generated model, with the computer generated model having a plurality of current ratios from which the at least one current ratio is selected and the one current ratio being a ratio of an inner electrical current to an outer electrical current. The method further includes applying the inner electrical current to the inner anode and the outer electrical current to the outer anode and adjusting the inner and outer electrical currents to incorporate the one current ratio. The generating of the computer generated model with the simulation computer program includes using a first iterative loop to determine a potential field in the anode chamber.

Abstract: Numerous embodiments of an apparatus and method of a dielectric material having a low dielectric constant and good mechanical strength are described. In one embodiment a dielectric material having multiple porous regions is disposed over a substrate. A caged structure is bridged within the plurality of pores. In one particular embodiment, the caged structure may be carborane or a carborane derivative.

Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a porous dielectric layer comprising at least one active end group, and bonding at least one large atomic radii species to replace the at least one active end group, wherein a local swelling may be formed within a portion of the porous dielectric.

Abstract: A slurry for use in a chemical mechanical polishing process for planarizing copper-based metal structures on a substrate comprises an oxidizer, an organic complexing agent, surfactants, and a plurality of copper-based metal abrasive particles, wherein the copper in the copper-based metal is capable of dissolving into the slurry and forming copper ion complexes. During the chemical mechanical polishing process, the copper removal rate may be selectively increased by increasing the concentration of copper metal abrasive particles in the slurry, and the copper removal rate may be selectively decreased by decreasing the concentration of copper metal abrasive particles in the slurry.

Abstract: Numerous embodiments of an apparatus and method of a dielectric material having a low dielectric constant and good mechanical strength are described. In one embodiment a dielectric material having multiple porous regions is disposed over a substrate. A caged structure is bridged within the plurality of pores. In one particular embodiment, the caged structure may be carborane or a carborane derivative.

Abstract: An apparatus for polishing a wafer comprising a rotatable polishing pad having a center of rotation and a rinse delivery conduit positioned adjacent to the polishing pad and substantially in radial alignment with the center. The rinse delivery conduit includes a plurality of nozzles to dispense a rinsing liquid. In one embodiment, the plurality of nozzles are configured and positioned to generate a higher flow rate of the rinsing liquid at the end of the rinse delivery conduit proximate to the center than at the end of the rinse delivery conduit distal to the center. In another embodiment, the rinse delivery conduit has a proximal end which is substantially adjacent the center and the distal end which is approximately adjacent an outer periphery of the pad.

Abstract: An electronic device that includes a molecular sieve layer is described herein. The molecular sieve layer may be used as a high mechanical strength, low dielectric constant insulating layer.

Abstract: A method for selecting and forming a low-k, relatively high E porous ceramic film in a semiconductor device is described. A ceramic material is selected having a relatively high Young's modulus and relatively lower dielectric constant. The k is reduced by making the film porous.

Abstract: An apparatus for polishing a wafer comprising a rotatable polishing pad having a center of rotation and a rinse delivery conduit positioned adjacent to the polishing pad and substantially in radial alignment with the center. The rinse delivery conduit includes a plurality of nozzles to dispense a rinsing liquid. In one embodiment, the plurality of nozzles are configured and positioned to generate a higher flow rate of the rinsing liquid at the end of the rinse delivery conduit proximate to the center than at the end of the rinse delivery conduit distal to the center. In another embodiment, the rinse delivery conduit has a proximal end which is substantially adjacent the center and the distal end which is approximately adjacent an outer periphery of the pad.

Abstract: An apparatus with a plating container with at least two anodes is described herein.

Abstract: An apparatus for polishing a wafer comprising a rotatable polishing pad having a center of rotation and a rinse delivery conduit positioned adjacent to the polishing pad and substantially in radial alignment with the center. The rinse delivery conduit includes a plurality of nozzles to dispense a rinsing liquid. In one embodiment, the plurality of nozzles are configured and positioned to generate a higher flow rate of the rinsing liquid at the end of the rinse delivery conduit proximate to the center than at the end of the rinse delivery conduit distal to the center. In another embodiment, the rinse delivery conduit has a proximal end which is substantially adjacent the center and the distal end which is approximately adjacent an outer periphery of the pad.

Abstract: An apparatus for polishing a wafer comprising a rotatable polishing pad having a center of rotation and a rinse delivery conduit positioned adjacent to the polishing pad and substantially in radial alignment with the center. The rinse delivery conduit includes a plurality of nozzles to dispense a rinsing liquid. In one embodiment, the plurality of nozzles are configured and positioned to generate a higher flow rate of the rinsing liquid at the end of the rinse delivery conduit proximate to the center than at the end of the rinse delivery conduit distal to the center. In another embodiment, the rinse delivery conduit has a proximal end which is substantially adjacent the center and the distal end which is approximately adjacent an outer periphery of the pad.

Abstract: A method is provided for creating a polish pad. This may involve determining a design layout of a wafer. The design layout may include a distribution of metal line features on the wafer. A polish pad design may be created/determined based on the determined layer. The polish pad may have asperities having a width greater than a width of metal line features of the wafer.

Abstract: An efficient TCAD tool to analyze the variation of topography and thickness of interconnects and components of integrated circuits introduced by multiple-layer chemical-mechanical planarization (CMP). Contact stress distribution is determined on all scales as a function of topography. A formulation is used relating the pad deformation and therefore stress directly to pattern topography ({d}), and the pad mechanical properties. The 3-dimensional stress and deformation field is described, along with representation of the statistical pad roughness and slurry thickness information. These process conditions are also functions of the surface topography and contact regimes. The stress-topography relationship is represented as [A]{P}={d}, where [A] is the influence coefficient matrix determined by the contact mechanics, and {P} and {d} represent local stress and topography on patterns.

Abstract: A cyclotene chemical structure may be modified to reduce its curing temperature. With the reduced curing temperature, the material may be highly advantageous as an underfill material for surface nonpackaging.

Abstract: A cyclotene chemical structure may be modified to reduce its curing temperature. With the reduced curing temperature, the material may be highly advantageous as an underfill material for surface nonpackaging.

Abstract: An efficient TCAD tool to analyze the variation of topography and thickness of interconnects and components of integrated circuits introduced by multiple-layer chemical-mechanical planarization (CMP). Contact stress distribution is determined on all scales as a function of topography. A formulation is used relating the pad deformation and therefore stress directly to pattern topography ({d}), and the pad mechanical properties. The 3-dimensional stress and deformation field is described, along with representation of the statistical pad roughness and slurry thickness information. These process conditions are also functions of the surface topography and contact regimes. The stress-topography relationship is represented as [A]{P}={d}, where [A] is the influence coefficient matrix determined by the contact mechanics, and {P} and {d} represent local stress and topography on patterns.

Abstract: A method is provided for creating a polish pad. This may involve determining a design layout of a wafer. The design layout may include a distribution of metal line features on the wafer. A polish pad design may be created/determined based on the determined layer. The polish pad may have asperities having a width greater than a width of metal line features of the wafer.