Patents by Inventor Sadatoshi Murakami

Sadatoshi Murakami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210217755
    Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.
    Type: Application
    Filed: March 26, 2021
    Publication date: July 15, 2021
    Inventors: Tomoo HISHIDA, Sadatoshi MURAKAMI, Ryota KATSUMATA, Masao IWASE
  • Patent number: 11031306
    Abstract: According to one embodiment, a quality control method of a position measurement light source includes irradiating light of the position measurement light source on a plurality of marks having different heights and measuring a relationship between the height of the mark and an intensity of light reflected by the mark. The quality control method includes identifying a wavelength of the position measurement light source by comparing measurement data acquired by the measuring to reference data of a relationship between the height of the mark and an intensity of reflected light for each of a plurality of wavelengths.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: June 8, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Miki Toshima, Sadatoshi Murakami
  • Patent number: 10971511
    Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: April 6, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tomoo Hishida, Sadatoshi Murakami, Ryota Katsumata, Masao Iwase
  • Publication number: 20200212053
    Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.
    Type: Application
    Filed: March 11, 2020
    Publication date: July 2, 2020
    Inventors: Tomoo HISHIDA, Sadatoshi MURAKAMI, Ryota KATSUMATA, Masao IWASE
  • Patent number: 10622372
    Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: April 14, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tomoo Hishida, Sadatoshi Murakami, Ryota Katsumata, Masao Iwase
  • Publication number: 20190295902
    Abstract: According to one embodiment, a quality control method of a position measurement light source includes irradiating light of the position measurement light source on a plurality of marks having different heights and measuring a relationship between the height of the mark and an intensity of light reflected by the mark. The quality control method includes identifying a wavelength of the position measurement light source by comparing measurement data acquired by the measuring to reference data of a relationship between the height of the mark and an intensity of reflected light for each of a plurality of wavelengths.
    Type: Application
    Filed: September 11, 2018
    Publication date: September 26, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Miki Toshima, Sadatoshi Murakami
  • Publication number: 20190164979
    Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.
    Type: Application
    Filed: January 30, 2019
    Publication date: May 30, 2019
    Inventors: Tomoo HISHIDA, Sadatoshi MURAKAMI, Ryota KATSUMATA, Masao IWASE
  • Patent number: 10199387
    Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: February 5, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Tomoo Hishida, Sadatoshi Murakami, Ryota Katsumata, Masao Iwase
  • Publication number: 20180358368
    Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.
    Type: Application
    Filed: August 17, 2018
    Publication date: December 13, 2018
    Inventors: Tomoo HISHIDA, Sadatoshi MURAKAMI, Ryota KATSUMATA, Masao IWASE
  • Patent number: 10056403
    Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: August 21, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Tomoo Hishida, Sadatoshi Murakami, Ryota Katsumata, Masao Iwase
  • Publication number: 20180006042
    Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.
    Type: Application
    Filed: September 18, 2017
    Publication date: January 4, 2018
    Inventors: Tomoo HISHIDA, Sadatoshi MURAKAMI, Ryota KATSUMATA, Masao IWASE
  • Publication number: 20170364624
    Abstract: A method of calculating a form according to an embodiment relates to a method of calculating a processed depth of a material to be etched when the material to be etched is etched using a mask material. The method comprises calculating a first opening solid angle ?1 based on an opening of a mask pattern, the first opening solid angle ?1 defining an incident quantity of ions contributing to etching, and calculating a second opening solid angle ?2 based on an opening of a mask pattern, the second opening solid angle ?2 defining an incident quantity of depositions. A processed depth at a process point where the material to be etched is etched is calculated based on a linear equation using the first opening solid angle ?1 and the second opening solid angle ?2 as variables.
    Type: Application
    Filed: March 22, 2017
    Publication date: December 21, 2017
    Applicant: Toshiba Memory Corporation
    Inventor: Sadatoshi MURAKAMI
  • Patent number: 9786556
    Abstract: According to an embodiment, a manufacturing method of a semiconductor device includes forming, on a film to be processed, a plurality of first core material patterns and a plurality of second core material patterns. Each of the second core material patterns is drawn from an end portion of the corresponding first core material pattern. The manufacturing method includes forming an opening pattern having one or a plurality of openings in the second core material pattern so that a first distance and a second distance are less than a predetermined distance. The first distance is a distance between an edge of the second core material pattern at a side of an adjacent first core material pattern and the opening pattern. The second distance is a distance between an edge of the second core material pattern at a side of an adjacent second core material pattern and the opening pattern.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: October 10, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Weiting Wang, Fumiharu Nakajima, Yoko Yokoyama, Sadatoshi Murakami
  • Patent number: 9768188
    Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: September 19, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tomoo Hishida, Sadatoshi Murakami, Ryota Katsumata, Masao Iwase
  • Publication number: 20170133267
    Abstract: According to an embodiment, a manufacturing method of a semiconductor device includes forming, on a film to be processed, a plurality of first core material patterns and a plurality of second core material patterns. Each of the second core material patterns is drawn from an end portion of the corresponding first core material pattern. The manufacturing method includes forming an opening pattern having one or a plurality of openings in the second core material pattern so that a first distance and a second distance are less than a predetermined distance. The first distance is a distance between an edge of the second core material pattern at a side of an adjacent first core material pattern and the opening pattern. The second distance is a distance between an edge of the second core material pattern at a side of an adjacent second core material pattern and the opening pattern.
    Type: Application
    Filed: January 19, 2017
    Publication date: May 11, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Weiting Wang, Fumiharu Nakajima, Yoko Yokoyama, Sadatoshi Murakami
  • Patent number: 9646988
    Abstract: According to one embodiment, a semiconductor memory device includes a substrate; a stacked body provided on the substrate, the stacked body including a plurality of electrode layers and a first step portion, the first step portion having the plurality of electrode layers provided stepwise; a column provided in a region of the stacked body other than a region in the first step portion provided; and a plurality of insulating portions provided in the first step portion. The stacked body includes a metal silicide portion provided between the plurality of insulating portions and the plurality of electrode layers, a plurality of terraces provided on a top surface of each of the plurality of electrode layers of the first step portion, and a plurality of contact portions provided on the plurality of terraces.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: May 9, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Sadatoshi Murakami, Hiroomi Nakajima
  • Patent number: 9646982
    Abstract: According to an embodiment, a manufacturing method of a semiconductor device includes forming, on a film to be processed, a plurality of first core material patterns and a plurality of second core material patterns. Each of the second core material patterns is drawn from an end portion of the corresponding first core material pattern. The manufacturing method includes forming an opening pattern having one or a plurality of openings in the second core material pattern so that a first distance and a second distance are less than a predetermined distance. The first distance is a distance between an edge of the second core material pattern at a side of an adjacent first core material pattern and the opening pattern. The second distance is a distance between an edge of the second core material pattern at a side of an adjacent second core material pattern and the opening pattern.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: May 9, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Weiting Wang, Fumiharu Nakajima, Yoko Yokoyama, Sadatoshi Murakami
  • Publication number: 20170062441
    Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.
    Type: Application
    Filed: November 11, 2016
    Publication date: March 2, 2017
    Inventors: Tomoo HISHIDA, Sadatoshi MURAKAMI, Ryota KATSUMATA, Masao IWASE
  • Patent number: 9502299
    Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: November 22, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomoo Hishida, Sadatoshi Murakami, Ryota Katsumata, Masao Iwase
  • Publication number: 20160268297
    Abstract: According to one embodiment, a semiconductor memory device includes a substrate; a stacked body provided on the substrate, the stacked body including a plurality of electrode layers and a first step portion, the first step portion having the plurality of electrode layers provided stepwise; a column provided in a region of the stacked body other than a region in the first step portion provided; and a plurality of insulating portions provided in the first step portion. The stacked body includes a metal silicide portion provided between the plurality of insulating portions and the plurality of electrode layers, a plurality of terraces provided on a top surface of each of the plurality of electrode layers of the first step portion, and a plurality of contact portions provided on the plurality of terraces.
    Type: Application
    Filed: September 4, 2015
    Publication date: September 15, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Sadatoshi MURAKAMI, Hiroomi NAKAJIMA