Patents by Inventor Sadatoshi Murakami
Sadatoshi Murakami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11974439Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.Type: GrantFiled: November 21, 2022Date of Patent: April 30, 2024Assignee: KIOXIA CORPORATIONInventors: Tomoo Hishida, Sadatoshi Murakami, Ryota Katsumata, Masao Iwase
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Publication number: 20230088310Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.Type: ApplicationFiled: November 21, 2022Publication date: March 23, 2023Inventors: Tomoo HISHIDA, Sadatoshi MURAKAMI, Ryota KATSUMATA, Masao IWASE
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Patent number: 11552095Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.Type: GrantFiled: March 26, 2021Date of Patent: January 10, 2023Assignee: KIOXIA CORPORATIONInventors: Tomoo Hishida, Sadatoshi Murakami, Ryota Katsumata, Masao Iwase
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Publication number: 20210217755Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.Type: ApplicationFiled: March 26, 2021Publication date: July 15, 2021Inventors: Tomoo HISHIDA, Sadatoshi MURAKAMI, Ryota KATSUMATA, Masao IWASE
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Patent number: 11031306Abstract: According to one embodiment, a quality control method of a position measurement light source includes irradiating light of the position measurement light source on a plurality of marks having different heights and measuring a relationship between the height of the mark and an intensity of light reflected by the mark. The quality control method includes identifying a wavelength of the position measurement light source by comparing measurement data acquired by the measuring to reference data of a relationship between the height of the mark and an intensity of reflected light for each of a plurality of wavelengths.Type: GrantFiled: September 11, 2018Date of Patent: June 8, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Miki Toshima, Sadatoshi Murakami
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Patent number: 10971511Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.Type: GrantFiled: March 11, 2020Date of Patent: April 6, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tomoo Hishida, Sadatoshi Murakami, Ryota Katsumata, Masao Iwase
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Publication number: 20200212053Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.Type: ApplicationFiled: March 11, 2020Publication date: July 2, 2020Inventors: Tomoo HISHIDA, Sadatoshi MURAKAMI, Ryota KATSUMATA, Masao IWASE
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Patent number: 10622372Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.Type: GrantFiled: January 30, 2019Date of Patent: April 14, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tomoo Hishida, Sadatoshi Murakami, Ryota Katsumata, Masao Iwase
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Publication number: 20190295902Abstract: According to one embodiment, a quality control method of a position measurement light source includes irradiating light of the position measurement light source on a plurality of marks having different heights and measuring a relationship between the height of the mark and an intensity of light reflected by the mark. The quality control method includes identifying a wavelength of the position measurement light source by comparing measurement data acquired by the measuring to reference data of a relationship between the height of the mark and an intensity of reflected light for each of a plurality of wavelengths.Type: ApplicationFiled: September 11, 2018Publication date: September 26, 2019Applicant: Toshiba Memory CorporationInventors: Miki Toshima, Sadatoshi Murakami
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Publication number: 20190164979Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.Type: ApplicationFiled: January 30, 2019Publication date: May 30, 2019Inventors: Tomoo HISHIDA, Sadatoshi MURAKAMI, Ryota KATSUMATA, Masao IWASE
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Patent number: 10199387Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.Type: GrantFiled: August 17, 2018Date of Patent: February 5, 2019Assignee: Toshiba Memory CorporationInventors: Tomoo Hishida, Sadatoshi Murakami, Ryota Katsumata, Masao Iwase
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Publication number: 20180358368Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.Type: ApplicationFiled: August 17, 2018Publication date: December 13, 2018Inventors: Tomoo HISHIDA, Sadatoshi MURAKAMI, Ryota KATSUMATA, Masao IWASE
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Patent number: 10056403Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.Type: GrantFiled: September 18, 2017Date of Patent: August 21, 2018Assignee: Toshiba Memory CorporationInventors: Tomoo Hishida, Sadatoshi Murakami, Ryota Katsumata, Masao Iwase
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Publication number: 20180006042Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.Type: ApplicationFiled: September 18, 2017Publication date: January 4, 2018Inventors: Tomoo HISHIDA, Sadatoshi MURAKAMI, Ryota KATSUMATA, Masao IWASE
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METHOD OF CALCULATING PROCESSED DEPTH AND STORAGE MEDIUM STORING PROCESSED-DEPTH CALCULATING PROGRAM
Publication number: 20170364624Abstract: A method of calculating a form according to an embodiment relates to a method of calculating a processed depth of a material to be etched when the material to be etched is etched using a mask material. The method comprises calculating a first opening solid angle ?1 based on an opening of a mask pattern, the first opening solid angle ?1 defining an incident quantity of ions contributing to etching, and calculating a second opening solid angle ?2 based on an opening of a mask pattern, the second opening solid angle ?2 defining an incident quantity of depositions. A processed depth at a process point where the material to be etched is etched is calculated based on a linear equation using the first opening solid angle ?1 and the second opening solid angle ?2 as variables.Type: ApplicationFiled: March 22, 2017Publication date: December 21, 2017Applicant: Toshiba Memory CorporationInventor: Sadatoshi MURAKAMI -
Patent number: 9786556Abstract: According to an embodiment, a manufacturing method of a semiconductor device includes forming, on a film to be processed, a plurality of first core material patterns and a plurality of second core material patterns. Each of the second core material patterns is drawn from an end portion of the corresponding first core material pattern. The manufacturing method includes forming an opening pattern having one or a plurality of openings in the second core material pattern so that a first distance and a second distance are less than a predetermined distance. The first distance is a distance between an edge of the second core material pattern at a side of an adjacent first core material pattern and the opening pattern. The second distance is a distance between an edge of the second core material pattern at a side of an adjacent second core material pattern and the opening pattern.Type: GrantFiled: January 19, 2017Date of Patent: October 10, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Weiting Wang, Fumiharu Nakajima, Yoko Yokoyama, Sadatoshi Murakami
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Patent number: 9768188Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.Type: GrantFiled: November 11, 2016Date of Patent: September 19, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tomoo Hishida, Sadatoshi Murakami, Ryota Katsumata, Masao Iwase
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Publication number: 20170133267Abstract: According to an embodiment, a manufacturing method of a semiconductor device includes forming, on a film to be processed, a plurality of first core material patterns and a plurality of second core material patterns. Each of the second core material patterns is drawn from an end portion of the corresponding first core material pattern. The manufacturing method includes forming an opening pattern having one or a plurality of openings in the second core material pattern so that a first distance and a second distance are less than a predetermined distance. The first distance is a distance between an edge of the second core material pattern at a side of an adjacent first core material pattern and the opening pattern. The second distance is a distance between an edge of the second core material pattern at a side of an adjacent second core material pattern and the opening pattern.Type: ApplicationFiled: January 19, 2017Publication date: May 11, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Weiting Wang, Fumiharu Nakajima, Yoko Yokoyama, Sadatoshi Murakami
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Patent number: 9646982Abstract: According to an embodiment, a manufacturing method of a semiconductor device includes forming, on a film to be processed, a plurality of first core material patterns and a plurality of second core material patterns. Each of the second core material patterns is drawn from an end portion of the corresponding first core material pattern. The manufacturing method includes forming an opening pattern having one or a plurality of openings in the second core material pattern so that a first distance and a second distance are less than a predetermined distance. The first distance is a distance between an edge of the second core material pattern at a side of an adjacent first core material pattern and the opening pattern. The second distance is a distance between an edge of the second core material pattern at a side of an adjacent second core material pattern and the opening pattern.Type: GrantFiled: February 26, 2015Date of Patent: May 9, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Weiting Wang, Fumiharu Nakajima, Yoko Yokoyama, Sadatoshi Murakami
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Patent number: 9646988Abstract: According to one embodiment, a semiconductor memory device includes a substrate; a stacked body provided on the substrate, the stacked body including a plurality of electrode layers and a first step portion, the first step portion having the plurality of electrode layers provided stepwise; a column provided in a region of the stacked body other than a region in the first step portion provided; and a plurality of insulating portions provided in the first step portion. The stacked body includes a metal silicide portion provided between the plurality of insulating portions and the plurality of electrode layers, a plurality of terraces provided on a top surface of each of the plurality of electrode layers of the first step portion, and a plurality of contact portions provided on the plurality of terraces.Type: GrantFiled: September 4, 2015Date of Patent: May 9, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Sadatoshi Murakami, Hiroomi Nakajima