Patents by Inventor Sadatoshi Murakami
Sadatoshi Murakami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170062441Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.Type: ApplicationFiled: November 11, 2016Publication date: March 2, 2017Inventors: Tomoo HISHIDA, Sadatoshi MURAKAMI, Ryota KATSUMATA, Masao IWASE
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Patent number: 9502299Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.Type: GrantFiled: September 2, 2014Date of Patent: November 22, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Tomoo Hishida, Sadatoshi Murakami, Ryota Katsumata, Masao Iwase
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Publication number: 20160268297Abstract: According to one embodiment, a semiconductor memory device includes a substrate; a stacked body provided on the substrate, the stacked body including a plurality of electrode layers and a first step portion, the first step portion having the plurality of electrode layers provided stepwise; a column provided in a region of the stacked body other than a region in the first step portion provided; and a plurality of insulating portions provided in the first step portion. The stacked body includes a metal silicide portion provided between the plurality of insulating portions and the plurality of electrode layers, a plurality of terraces provided on a top surface of each of the plurality of electrode layers of the first step portion, and a plurality of contact portions provided on the plurality of terraces.Type: ApplicationFiled: September 4, 2015Publication date: September 15, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Sadatoshi MURAKAMI, Hiroomi NAKAJIMA
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Publication number: 20160071859Abstract: According to an embodiment, a manufacturing method of a semiconductor device includes forming, on a film to be processed, a plurality of first core material patterns and a plurality of second core material patterns. Each of the second core material patterns is drawn from an end portion of the corresponding first core material pattern. The manufacturing method includes forming an opening pattern having one or a plurality of openings in the second core material pattern so that a first distance and a second distance are less than a predetermined distance. The first distance is a distance between an edge of the second core material pattern at a side of an adjacent first core material pattern and the opening pattern. The second distance is a distance between an edge of the second core material pattern at a side of an adjacent second core material pattern and the opening pattern.Type: ApplicationFiled: February 26, 2015Publication date: March 10, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Weiting WANG, Fumiharu Nakajima, Yoko Yokoyama, Sadatoshi Murakami
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Publication number: 20160070847Abstract: According to an embodiment, a pattern dimension calculation method includes setting a reference point on a first circuit pattern, calculating, as a size of area of an opposing pattern, a size of area of a range corresponding to the reference point of a second circuit pattern opposite to the reference point, and calculating a dimension of the first circuit pattern in accordance with the size of area of the opposing pattern.Type: ApplicationFiled: February 18, 2015Publication date: March 10, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takafumi TAGUCHI, Takashi ICHIKAWA, Sadatoshi MURAKAMI, Norihisa SUZUKI
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Publication number: 20150263024Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.Type: ApplicationFiled: September 2, 2014Publication date: September 17, 2015Inventors: Tomoo HISHIDA, Sadatoshi MURAKAMI, Ryota KATSUMATA, Masao IWASE
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Publication number: 20150263026Abstract: According to one embodiment, a semiconductor device includes: a substrate including silicon; and a first element provided on the substrate and extending in a thickness direction of the substrate, a center position of an end face on the substrate side of the first element and a center position of an end face on an opposite side of the substrate side of the first element being different in a direction parallel to a major surface of the substrate.Type: ApplicationFiled: July 25, 2014Publication date: September 17, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Yuko KONO, Ai Inoue, Toshiya Kotani, Chikaaki Kodama, Yasunobu Kai, Sadatoshi Murakami
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Patent number: 9136392Abstract: According to one embodiment, the underlying film includes a memory region including a first trench and a peripheral region including a second trench. The stacked body includes conductive layers and insulating layers alternately stacked on the underlying film. The channel body is provided in a pair of first holes and the first trench. The first holes pierce the stacked body to be connected to the first trench. The memory film includes a charge storage film provided between a side wall of the first hole and the channel body, and between an inner wall of the first trench and the channel body. The conductor is provided in a pair of second holes and the second trench. The second holes pierce the stacked body to be connected to the second trench.Type: GrantFiled: August 20, 2013Date of Patent: September 15, 2015Assignee: Kabushiki Kaisha ToshibaInventor: Sadatoshi Murakami
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Patent number: 9111963Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a plurality of pillars and a plurality of sidewall films on a stacked body including a plurality of electrode layers stacked alternately with a plurality of insulating layers. The pillars are arranged in a first direction and a second direction intersecting the first direction at different pitches in the first direction and the second direction. The sidewall films are provided on outer circumferential surfaces of the pillars to extend in the first direction to be linked in the first direction and separated in the second direction. The method includes making a slit to divide the stacked body in the second direction by etching the stacked body under a region between the sidewall films adjacent to each other in the second direction using the pillars and the sidewall films as a mask.Type: GrantFiled: August 20, 2013Date of Patent: August 18, 2015Assignee: Kabushiki Kaisha ToshibaInventor: Sadatoshi Murakami
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Publication number: 20140284686Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a plurality of pillars and a plurality of sidewall films on a stacked body including a plurality of electrode layers stacked alternately with a plurality of insulating layers. The pillars are arranged in a first direction and a second direction intersecting the first direction at different pitches in the first direction and the second direction. The sidewall films are provided on outer circumferential surfaces of the pillars to extend in the first direction to be linked in the first direction and separated in the second direction. The method includes making a slit to divide the stacked body in the second direction by etching the stacked body under a region between the sidewall films adjacent to each other in the second direction using the pillars and the sidewall films as a mask.Type: ApplicationFiled: August 20, 2013Publication date: September 25, 2014Applicant: Kabushiki Kaisha ToshibaInventor: Sadatoshi MURAKAMI
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Publication number: 20140284687Abstract: According to one embodiment, a nonvolatile memory device includes a plurality of electrodes provided on an under layer and arranged in parallel to the under layer, a semiconductor layer piercing one of the electrodes in the first direction, a memory film provided between the one of the electrodes and the semiconductor layer, and a bridge portion provided between the electrodes adjacent to each other. Each of the electrodes including a plurality of first layers having conductivity and a plurality of second layers having insulation properties, the first layers being stacked in a first direction perpendicular to the under layer, and each of the second layers being provided between the first layers adjacent to each other.Type: ApplicationFiled: August 20, 2013Publication date: September 25, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Sadatoshi MURAKAMI
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Patent number: 8749078Abstract: According to one embodiment, a semiconductor device includes a stacked body in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked. The semiconductor device includes a mark and a supporting unit. The mark is opened onto a surface of the stacked body. The supporting unit is provided around the mark. The supporting unit extends in a stacked direction of the stacked body. The supporting unit is in contact with at least a plurality of conductive layers.Type: GrantFiled: August 31, 2012Date of Patent: June 10, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Sadatoshi Murakami
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Publication number: 20140061754Abstract: According to one embodiment, the underlying film includes a memory region including a first trench and a peripheral region including a second trench. The stacked body includes conductive layers and insulating layers alternately stacked on the underlying film. The channel body is provided in a pair of first holes and the first trench. The first holes pierce the stacked body to be connected to the first trench. The memory film includes a charge storage film provided between a side wall of the first hole and the channel body, and between an inner wall of the first trench and the channel body. The conductor is provided in a pair of second holes and the second trench. The second holes pierce the stacked body to be connected to the second trench.Type: ApplicationFiled: August 20, 2013Publication date: March 6, 2014Applicant: Kabushiki Kaisha ToshibaInventor: Sadatoshi MURAKAMI
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Publication number: 20130234299Abstract: According to one embodiment, a_semiconductor device includes a stacked body in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked. The semiconductor device includes a mark and a supporting unit. The mark is opened onto a surface of the stacked body. The supporting unit is provided around the mark. The supporting unit extends in a stacked direction of the stacked body. The supporting unit is in contact with at least a plurality of conductive layers.Type: ApplicationFiled: August 31, 2012Publication date: September 12, 2013Applicant: Kabushiki Kaisha ToshibaInventor: Sadatoshi MURAKAMI
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Patent number: 5283542Abstract: A composition of matter is provided which comprises low-shrinkage, wet-type unsaturated polyester (B.M.C.) having high thermal conductivity, glass fibers, and a particulate aluminum nitride filler having high thermal conductivity. Also provided is an electrical component housing which possesses high thermal conductivity and heat dissipation properties including a body of a low-shrinkage, wet-type unsaturated polyester (B.M.C.) composition having high thermal conductivity.Type: GrantFiled: July 2, 1992Date of Patent: February 1, 1994Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Haruyuki Ochiai, Sadatoshi Murakami, Setsuo Hosogai
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Patent number: 5273193Abstract: A welding fuel tank has a magnet 3 disposed on the inside or outside thereof in the vicinity of a fuel pump 12 which is housed inside the fuel tank. The magnet collects magnetic spatter which remains inside the fuel tank after welding and prevents the spatter from entering the fuel pump. The magnet may be a permanent magnet or an electromagnet, and it may be disposed outside the pump or in the fuel filter of the fuel pump. A cleaning method for a welded fuel tank comprises introducing a magnet into a fuel tank after welding, vibrating the fuel tank so that the magnet will move about the inside of the fuel tank and collect magnetic spatter, and then removing the magnet and spatter from the fuel tank.Type: GrantFiled: March 3, 1989Date of Patent: December 28, 1993Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Sadatoshi Murakami, Satoru Yamasaki, Tatsumi Harada
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Patent number: 5085768Abstract: A 3 fuel tank has a magnet 3 disposed on the inside or outside thereof in the vicinity of a fuel pump 12 which is housed inside the fuel tank. The magnet collects magnetic spatter which remains inside the fuel tank after welding and prevents the spatter from entering the fuel pump. The magnet may be a permanent magnet or an electromagnet, and it may be disposed outside the pump or in the fuel filter of the fuel pump. A cleaning method for a welded fuel tank comprises introducing a magnet into a fuel tank after welding, vibrating the fuel tank so that the magnet will move about the inside of the fuel tank and collect magnetic spatter, and then removing the magnet and spatter from the fuel tank.Type: GrantFiled: October 31, 1990Date of Patent: February 4, 1992Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Sadatoshi Murakami, Satoru Yamasaki, Tatsumi Harada
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Patent number: 4839667Abstract: A platen for use in thermal printer of a type designed to effect a printing with the use of at least one thermal print head for printing on a recording medium positioned between the platen and the thermal print head, which platen comprises a generally elongated elastic body having an exterior surface adapted to be brought into contact with the heating elements of the thermal print head assembly with at least the recording medium intervening therebetween, and a layer of porous material lined on the exterior surface of the elastic body and having a hardness greater than that of the elastic body and also having a thermal conductivity lower than that of the elastic body. The thermal conductivity and the porosity of the layer of porous material may be within the range of 0.05 to 0.10 Kcal/m.sup.2 .multidot.hr.multidot..degree.C. and within the range of 50 to 95%, respectively.Type: GrantFiled: October 30, 1987Date of Patent: June 13, 1989Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Sadatoshi Murakami, Satoru Yamasaki, Masayuki Tanaka, Sayoko Hirata, Hiromi Morimoto, Kenji Nomura, Kenichiro Oka, Masaru Ohnishi
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Patent number: 4780729Abstract: A platen for use in a thermal printer of a type designed to effect printing with the use of at least one thermal print head for printing a recording medium positioned between the platen and the thermal print head, which platen comprises a generally elongated elastic body having an exterior surface adapted to be brought into contact with the heating elements of the thermal print head assembly with at least the recording medium intervening therebetween. At least the exterior surface of the elastic body is mixed with a mass of porous fine particles having a hardness greater than that of the elastic body and also having a thermal conductivity lower than that of the elastic body. The thermal conductivity and the porosity of the porous fine particles may be within the range of 0.04 to 0.09 Kcal/m.sup.2.hr..degree.C. and within the range of 60 to 95%, respectively.Type: GrantFiled: October 30, 1987Date of Patent: October 25, 1988Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Sadatoshi Murakami, Satoru Yamasaki, Kenji Nomura, Masayuki Tanaka, Kenichiro Oka, Masaru Ohnishi, Sayoko Hirata
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Patent number: 4733251Abstract: A thermal transfer printing method which is performed by the use of a thermal printer including a platen, a thermal print head having at least one heating element and a length of ink carrier ribbon with the recording medium positioned between the thermal print head and the length of ink carrier ribbon, which ink carrier ribbon having a base film and an ink layer, which method includes the steps of pressing the ink carrier ribbon against the platen by the thermal print head with the ink layer brought in contact with the recording medium, heating the heating element to cause that portion of the ink layer, which is aligned with the heating element, to fuse, and causing that portion of the ink layer so fused to partially transfer onto the recording medium when a cohesive force acting internally of the ink layer becomes smaller than an adhesive force acting between the ink layer and the recording medium and, at the same time, smaller than a adhesive force acting between the ink layer and the base film, whereby theType: GrantFiled: July 2, 1987Date of Patent: March 22, 1988Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Sadatoshi Murakami, Satoru Yamasaki, Masaru Ohnishi, Kenji Nomura, Masayuki Tanaka, Sayoko Hirata