Abstract: A semiconductor integrated circuit includes a plurality of output transistors each controlling the magnitude of an output voltage relative to the magnitude of a load current according to a control value indicated by an impedance control signal applied to a control terminal, a voltage monitor circuit outputting an output voltage monitor value indicating a voltage value of the output voltage, and a control circuit controlling the magnitude of the control value according to the magnitude of an error value between a reference voltage indicating a target value of the output voltage and the output voltage monitor value, and controls based on the control value whether any of such transistors be brought to a conducting state. The control circuit increases a change step of the control value relative to the error value during a predetermined period according to prenotification signals for notifying a change of the load current in advance.

Abstract: A semiconductor integrated circuit includes a plurality of output transistors each controlling the magnitude of an output voltage relative to the magnitude of a load current according to a control value indicated by an impedance control signal applied to a control terminal, a voltage monitor circuit outputting an output voltage monitor value indicating a voltage value of the output voltage, and a control circuit controlling the magnitude of the control value according to the magnitude of an error value between a reference voltage indicating a target value of the output voltage and the output voltage monitor value, and controls based on the control value whether any of such transistors be brought to a conducting state. The control circuit increases a change step of the control value relative to the error value during a predetermined period according to prenotification signals for notifying a change of the load current in advance.

Abstract: A power-supply sequence-free electronic circuit is realized without the increase of the number of power supply detectors for detecting the rising of the power supply. The electronic circuit operated by supplying three or more types of power supply voltages to the ground voltage of the circuit generates a first detection signal indicating whether any one of other power supply voltages does not rise by a first detection circuit which is operated with a predetermined power supply voltage as an operation power supply. The electronic circuit generates a second detection signal indicating whether the predetermined power supply voltage rises by a second detection circuit which is provided for each of the other power supply voltages and operated with one power supply voltage of the other power supply voltages as an operation power supply.

Abstract: By using a small number of needles and contact terminals at burn-in, electric contact check is performed between each needle and each terminal provided in each semiconductor chip, and thereby the yield of assembled products can be improved. A packaging structure in which, for example, a volatile memory chip and a nonvolatile memory chip are formed is assembled in accordance with a production scheme in which burn-in of each memory chip is performed while still under the state of a semiconductor wafer, and by forming the packaged structure using the good volatile memory chip subjected to burn-in and likewise, also, the nonvolatile memory chip. At this burn-in, contact check is performed by bringing a needle, provided in a burn-in board, into contact with, for example, six test-only signal terminals of a test circuit formed on each semiconductor chip.

Abstract: By using a small number of needles and contact terminals at burn-in, electric contact check is performed between each needle and each terminal provided in each semiconductor chip, and thereby the yield of assembled products can be improved. A packaging structure in which, for example, a volatile memory chip and a nonvolatile memory chip are formed is assembled in accordance with a production scheme in which burn-in of each memory chip is performed while still under the state of a semiconductor wafer, and by forming the packaged structure using the good volatile memory chip subjected to burn-in and likewise, also, the nonvolatile memory chip. At this burn-in, contact check is performed by bringing a needle, provided in a burn-in board, into contact with, for example, six test-only signal terminals of a test circuit formed on each semiconductor chip.

Abstract: By using a small number of needles and contact terminals at burn-in, electric contact check is performed between each needle and each terminal provided in each semiconductor chip, and thereby the yield of assembled products can be improved. A packaging structure in which, for example, a volatile memory chip and a nonvolatile memory chip are formed is assembled in accordance with a production scheme in which burn-in of each memory chip is performed while still under the state of a semiconductor wafer, and by forming the packaged structure using the good volatile memory chip subjected to burn-in and likewise, also, the nonvolatile memory chip. At this burn-in, contact check is performed by bringing a needle, provided in a burn-in board, into contact with, for example, six test-only signal terminals of a test circuit formed on each semiconductor chip.

Abstract: The semiconductor device of the invention achieves a high-speed memory access. When the semiconductor device is configured to include a microprocessor and a semiconductor memory, the microprocessor includes an input/output buffer for system side that is made capable of exchanging signals with the outside by being supplied with a power supply voltage. The semiconductor memory includes an internal power supply circuit that takes in the power supply voltage as a reference voltage, and generates an internal power supply voltage being substantially equal to the power supply voltage; and it also includes an input/output buffer for memory side that is made capable of exchanging signals with the input/output buffer for system side by being supplied with the internal power supply voltage. This circuit configuration saves the level shifting on the microprocessor side, and realizes a high-speed access to the semiconductor memory from the microprocessor.

Abstract: The present invention provides, in a memory which stacks a plurality of large-capacity SRAM chips or in a large-capacity SRAM chip which is mounted on a system LSI, the SRAM chips which can be easily stacked and facilitate bonding. Address pads which supply predetermined address signals to circuit blocks from the outside and data input/output pads which input/output data with respect to the circuit block are formed over a semiconductor chip. The data input/output pads are arranged along a first side of the semiconductor chip, the address pads are arranged along a second side which shares one of corners of the semiconductor chip with the first side, and the data input/output pads are not arranged on the second side. Due to such a constitution, by arranging the address pads on one side of the chip and the data input/output pads on another side of the chip in a concentrated manner, stacking and bonding of the chips are facilitated.

Abstract: A Synchronous Dynamic Random Access Memory (SDRAM) has its operation mode selected to be the Single Data Rate (SDR) mode in response to the first state of the external terminal (OPT), thereby releasing data, which has been read out of a memory mat, in response to a clock signal produced by a clock regenerating circuit having a function of comparing the phases of the input and output of the circuit, or selected to be the Double Data Rate (DDR) mode in response to the second state of the external terminal (OPT), thereby releasing data, which has been read out of the memory mat, in response to a clock signal produced by a clock signal generation circuit in synchronism with an external clock. In the SDR mode, data are transferred via data lines in SDRAM unidirectionally and in the DDR mode, data are transferred via the data lines bidirectionally.

Abstract: By using a small number of needles and contact terminals at burn-in, electric contact check is performed between each needle and each terminal provided in each semiconductor chip, and thereby the yield of assembled products can be improved. A packaging structure in which, for example, a volatile memory chip and a nonvolatile memory chip are formed is assembled in accordance with a production scheme in which burn-in of each memory chip is performed while still under the state of a semiconductor wafer, and by forming the packaged structure using the good volatile memory chip subjected to burn-in and likewise, also, the nonvolatile memory chip. At this burn-in, contact check is performed by bringing a needle, provided in a burn-in board, into contact with, for example, six test-only signal terminals of a test circuit formed on each semiconductor chip.

Abstract: A plurality of unit areas having one to a plurality of MOSFETs for implementing specific logic circuits are placed in a first direction. A first interconnection extending in the first direction is formed over each unit area. A second interconnection extending in the first direction is formed along the plurality of unit areas and outside the unit areas. Wiring dedicated areas provided with a third interconnection extending in a second direction intersecting the first direction are respectively provided between the adjacent unit areas. A logic circuit formed in each unit area has both a first connection form connected to the first interconnection and a second connection form connected to the third interconnection, via the second interconnection, according to combinations with the wiring dedicated areas adjacent thereto, as needed.

Abstract: A semiconductor memory device of a DDR configuration improved in glitch immunity and the convenience of use is to be provided. It is a dynamic type RAM the operation of whose internal circuit is controlled in synchronism with a clock signal; an input circuit is provided in which a second clock signal inputted when in write operation is used to take in a plurality of write data serially inputted in response to that signal into a plurality of first latch circuits, and said first clock signal is used to take the write data taken into the first latch circuits into the second latch circuit to convey them to an input/output data bus; a logic circuit is provided to mask, in accordance with the logic of the first clock signal and the second clock signal, any noise arising at the end of the second clock signal, and a third clock signal is generated and supplied to the first latch circuits which output the write data to at least the input of the second latch circuits.

Abstract: An SDRAM has its operation mode selected to be the SDR mode in response to the first state of the external terminal (OPT), thereby releasing data, which has been read out of a memory mat, in response to a clock signal produced by a clock regenerating circuit having a function of comparing the phases of the input and output of the circuit, or selected to be the DDR mode in response to the second state of the external terminal (OPT), thereby releasing data, which has been read out of the memory mat, in response to a clock signal produced by a clock signal generation circuit in synchronism with an external clock signal.

Abstract: A static random access memory comprising memory cells each composed of transfer MISFETs controlled by word lines and of a flip-flop circuit made of driver MISFETs and load MISFETs. The top of the load MISFETs is covered with supply voltage lines so that capacitor elements of a stacked structure are formed between the gate electrodes of the load MISFETs and the supply voltage lines.

Abstract: A Synchronous Dynamic Random Access Memory (SDRAM) has its operation mode selected to be the Single Data Rate (SDR) mode in response to the first state of the external terminal (OPT), thereby releasing data, which has been read out of a memory mat, in response to a clock signal produced by a clock regenerating circuit having a function of comparing the phases of the input and output of the circuit, or selected to be the Double Data Rate (DDR) mode in response to the second state of the external terminal (OPT), thereby releasing data, which has been read out of the memory mat, in response to a clock signal produced by a clock signal generation circuit in synchronism with an external clock. In the SDR mode, data are transferred via data lines in SDRAM unidirectionally and in the DDR mode, data are transferred via the data lines bidirectionally.

Abstract: Differential amplifier circuits that receive input signals fed through external terminals are served with a first operation voltage and a second operation voltage through a first switching MOSFET and a second switching MOSFET, said first and second switching MOSFETs are turned on by a bis voltage-generating circuit when said input signal is near a central voltage of said first and second operation voltages, control voltages are formed to turn either said first switching MOSFET or said second switching MOSFET on and to turn the other one off to produce a corresponding output signal when the input signal continuously assumes said first voltage or said second voltage for a predetermined period of time, thereby to supply an input signal of a first amplitude corresponding to said first operation voltage and said second operation voltage as well as an input signal of a second amplitude corresponding to a predetermined intermediate voltage between said first operation voltage and said second operation voltage.

Abstract: A semiconductor memory device of a DDR configuration improved in glitch immunity and the convenience of use is to be provided. It is a dynamic type RAM the operation of whose internal circuit is controlled in synchronism with a clock signal; an input circuit is provided in which a second clock signal inputted when in write operation is used to take in a plurality of write data serially inputted in response to that signal into a plurality of first latch circuits, and said first clock signal is used to take the write data taken into the first latch circuits into the second latch circuit to convey them to an input/output data bus; a logic circuit is provided to mask, in accordance with the logic of the first clock signal and the second clock signal, any noise arising at the end of the second clock signal, and a third clock signal is generated and supplied to the first latch circuits which output the write data to at least the input of the second latch circuits.

Abstract: A semiconductor memory device of a DDR configuration improved in glitch immunity and the convenience of use is to be provided. It is a dynamic type RAM the operation of whose internal circuit is controlled in synchronism with a clock signal; an input circuit is provided in which a second clock signal inputted when in write operation is used to take in a plurality of write data serially inputted in response to that signal into a plurality of first latch circuits, and said first clock signal is used to take the write data taken into the first latch circuits into the second latch circuit to convey them to an input/output data bus; a logic circuit is provided to mask, in accordance with the logic of the first clock signal and the second clock signal, any noise arising at the end of the second clock signal, and a third clock signal is generated and supplied to the first latch circuits which output the write data to at least the input of the second latch circuits.

Abstract: A plurality of unit areas having one to a plurality of MOSFETs for implementing specific logic circuits are placed in a first direction. A first interconnection extending in the first direction is formed over each unit area. A second interconnection extending in the first direction is formed along the plurality of unit areas and outside the unit areas. Wiring dedicated areas provided with a third interconnection extending in a second direction intersecting the first direction are respectively provided between the adjacent unit areas. A logic circuit formed in each unit area has both a first connection form connected to the first interconnection and a second connection form connected to the third interconnection, via the second interconnection, according to combinations with the wiring dedicated areas adjacent thereto, as needed.

Abstract: Differential amplifier circuits that receive input signals fed through external terminals are served with a first operation voltage and a second operation voltage through a first switching MOSFET and a second switching MOSFET, said first and second switching MOSFETs are turned on by a bis voltage-generating circuit when said input signal is near a central voltage of said first and second operation voltages, control voltages are formed to turn either said first switching MOSFET or said second switching MOSFET on and to turn the other one off to produce a corresponding output signal when the input signal continuously assumes said first voltage or said second voltage for a predetermined period of time, thereby to supply an input signal of a first amplitude corresponding to said first operation voltage and said second operation voltage as well as an input signal of a second amplitude corresponding to a predetermined intermediate voltage between said first operation voltage and said second operation voltage.