Patents by Inventor Sadayuki Morita
Sadayuki Morita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20020018396Abstract: An SDRAM has its operation mode selected to be the SDR mode in response to the first state of the external terminal (OPT), thereby releasing data, which has been read out of a memory mat, in response to a clock signal produced by a clock regenerating circuit having a function of comparing the phases of the input and output of the circuit, or selected to be the DDR mode in response to the second state of the external terminal (OPT), thereby releasing data, which has been read out of the memory mat, in response to a clock signal produced by a clock signal generation circuit in synchronism with an external clock signal.Type: ApplicationFiled: September 28, 2001Publication date: February 14, 2002Inventors: Sadayuki Morita, Takeshi Sakata, Satoru Hanzawa, Takahiro Sonoda, Haruko Tadokoro, Hiroshi Ichikawa, Osamu Nagashima
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Publication number: 20020009006Abstract: By using a few number of needles and a few number of contact terminals at burn-in, electric contact check is performed between each needle and each terminal provided in each semiconductor chip, and thereby the yield of assembled products can be improved. A MCP having a packaging structure in which a volatile SRAM semiconductor chip and a nonvolatile flash memory semiconductor chip are formed is assembled in accordance with steps S201 to S212 by performing burn-in of each semiconductor chip of the SRAM and the flash memory under the state of a semiconductor wafer, and by forming the good SRAM to be subjected to burn-in and the flash memory semiconductor chip. At this burn-in, contact check is performed by bringing a needle provided in a burn-in board, into contact with six test-only signal terminals of a test circuit formed on each semiconductor chip.Type: ApplicationFiled: July 17, 2001Publication date: January 24, 2002Inventors: Yoshikazu Saitoh, Sadayuki Morita, Takahiro Sonoda
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Patent number: 6339344Abstract: Differential amplifier circuits that receive input signals fed through external terminals are served with a first operation voltage and a second operation voltage through a first switching MOSFET and a second switching MOSFET, said first and second switching MOSFETs are turned on by a bias voltage-generating circuit when said input signal is near a central voltage of said first and second operation voltages, control voltages are formed to turn either said first switching MOSFET or said second switching MOSFET on and to turn the other one off to produce a corresponding output signal when the input signal continuously assumes said first voltage or said second voltage for a predetermined period of time, thereby to supply an input signal of a first amplitude corresponding to said first operation voltage and said second operation voltage as well as an input signal of a second amplitude corresponding to a predetermined intermediate voltage between said first operation voltage and said second operation voltage.Type: GrantFiled: February 2, 2000Date of Patent: January 15, 2002Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Takeshi Sakata, Hitoshi Tanaka, Osamu Nagashima, Masafumi Ohi, Sadayuki Morita
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Patent number: 6335901Abstract: An SDRAM has its operation mode selected to be the SDR mode in response to the first state of the external terminal (OPT), thereby releasing data, which has been read out of a memory mat, in response to a clock signal produced by a clock regenerating circuit having a function of comparing the phases of the input and output of the circuit, or selected to be the DDR mode in response to the second state of the external terminal (OPT), thereby releasing data, which has been read out of the memory mat, in response to a clock signal produced by a clock signal generation circuit in synchronism with an external clock signal.Type: GrantFiled: March 20, 2000Date of Patent: January 1, 2002Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Sadayuki Morita, Takeshi Sakata, Satoru Hanzawa, Takahiro Sonoda, Haruko Tadokoro, Hiroshi Ichikawa, Osamu Nagashima
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Patent number: 6307217Abstract: A static random access memory comprising memory cells each composed of transfer MISFETs controlled by word lines and of a flip-flop circuit made of driver MISFETs and load MISFETs. The top of the load MISFETs is covered with supply voltage lines so that capacitor elements of a stacked structure are formed between the gate electrodes of the load MISFETs and the supply voltage lines.Type: GrantFiled: January 14, 1994Date of Patent: October 23, 2001Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Shuji Ikeda, Satoshi Meguro, Kyoichiro Asayama, Eri Fujita, Koichiro Ishibashi, Toshiro Aoto, Sadayuki Morita, Atsuyoshi Koike, Masayuki Kojima, Yasuo Kiguchi, Kazuyuki Suko, Fumiyuki Kanai, Naotaka Hashimoto, Toshiaki Yamanaka
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Publication number: 20010023965Abstract: A static random access memory comprising memory cells each composed of transfer MISFETs controlled by word lines and of a flip-flop circuit made of driver MISFETs and load MISFETs. The top of the load MISFETs is covered with supply voltage lines so that capacitor elements of a stacked structure are formed between the gate electrodes of the load MISFETs and the supply voltage lines.Type: ApplicationFiled: May 17, 2001Publication date: September 27, 2001Inventors: Shuji Ikeda, Satoshi Meguro, Kyoichiro Asayama, Eri Fujita, Koichiro Ishibashi, Toshiro Aoto, Sadayuki Morita, Atsuyoshi Koike, Masayuki Kojima, Yasuo Kiguchi, Kazuyuki Suko, Fumiyuki Kanai, Naotaka Hashimoto, Toshiaki Yamanaka
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Patent number: 6274895Abstract: A plurality of unit areas having one to a plurality of MOSFETs for implementing specific logic circuits are placed in a first direction. A first interconnection extending in the first direction is formed over each unit area. A second interconnection extending in the first direction is formed along the plurality of unit areas and outside the unit areas. Wiring dedicated areas provided with a third interconnection extending in a second direction intersecting the first direction are respectively provided between the adjacent unit areas. A logic circuit formed in each unit area has both a first connection form connected to the first interconnection and a second connection form connected to the third interconnection via the second interconnection according to combinations with the wiring dedicated areas adjacent thereto as needed.Type: GrantFiled: August 27, 1999Date of Patent: August 14, 2001Assignees: Hitachi, LTD, Hitachi ULSI Systems Co., LTDInventors: Isamu Fujii, Kiyoshi Nakai, Yukihide Suzuki, Sadayuki Morita, Hidekazu Egawa, Katura Abe, Noriaki Sakamoto
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Patent number: 6271687Abstract: A sense amplifier, which is intended to reduce the output response time after it has received a small voltage difference until it delivers amplified output signals, consists of a latch circuit made up of a pair of CMOS inverters, a pair of NMOS transistors connected in parallel to the latch circuit, and a current source connected in series to the latch circuit and NMOS transistor pair. The NMOS transistors amplify a small voltage difference of input signals, and the inverters of the latch circuit further amplify the resulting voltage difference to produce the output signals. Based on a small voltage difference of input signals being amplified in two stages and the amplifying circuit being 2-stage serial connection of the current source and the NMOS transistor or CMOS inverter, the delay time of output response can be reduced.Type: GrantFiled: March 21, 2000Date of Patent: August 7, 2001Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Hiroshi Toyoshima, Masashige Harada, Tomohiro Nagano, Yoji Nishio, Atsushi Hiraishi, Kunihiro Komiyaji, Hideharu Yahata, Kenichi Fukui, Hirofumi Zushi, Takahiro Sonoda, Haruko Kawachino, Sadayuki Morita
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Patent number: 6046609Abstract: A sense amplifier, which is intended to reduce the output response time after it has received a small voltage difference until it delivers amplified output signals, consists of a latch circuit made up of a pair of CMOS inverters, a pair of NMOS transistors connected in parallel to the latch circuit, and a current source connected in series to the latch circuit and NMOS transistor pair. The NMOS transistors amplify a small voltage difference of input signals, and the inverters of the latch circuit further amplify the resulting voltage difference to produce the output signals. Based on is a small voltage difference of input signals being amplified in two stages and the amplifying circuit being a 2-stage serial connection of the current source and the NMOS transistor or CMOS inverter, the delay time of output response can be reduced.Type: GrantFiled: November 10, 1998Date of Patent: April 4, 2000Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Hiroshi Toyoshima, Masashige Harada, Tomohiro Nagano, Yoji Nishio, Atsushi Hiraishi, Kunihiro Komiyaji, Hideharu Yahata, Kenichi Fukui, Hirofumi Zushi, Takahiro Sonoda, Haruko Kawachino, Sadayuki Morita
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Patent number: 5963483Abstract: A synchronous memory unit which includes a plurality of input buffers for receiving address data, a plurality of input latches for holding and outputting address data from in the input buffers according to a clock signal, a plurality of decoders for decoding the address data from the input latches, and a memory cell array having a plurality of memory cells which store and output data signals via bit lines according to the address data decoded by the decoders. Also provided are a sense amplifier for amplifying the output data signals on the bit lines, a selector for selecting one of the amplified output data signals according to the address data decoded by the decoders, and a selector output latch for holding and outputting the amplified output data signal from the selector according to the clock signal. An output latch holds and outputs the amplified output data signal from the selector output latch according to the clock signal.Type: GrantFiled: August 14, 1998Date of Patent: October 5, 1999Assignee: Hitachi, Ltd.Inventors: Hideharu Yahata, Kenichi Fukui, Yoji Nishio, Atsushi Hiraishi, Sadayuki Morita
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Patent number: 5936909Abstract: A static RAM has plurality of memory mats each including a plurality of static memory cells formed in a matrix pattern at points of intersection between a plurality of word lines and a plurality of data lines. upon receipt of an address signal into an address register, an address selection circuit selects a memory cell in one of the memory mats, and connects the selected memory cell to a sense amplifier or a write amplifier furnished corresponding to the memory mat in question. At the same time, an address counter generates an address signal corresponding to the address signal by which one of the memory mats has been selected. When a burst mode is designated by a control signal, the address signal admitted to the address register is used to select a memory cell in a first memory mat. The selected memory cell is connected to the corresponding sense amplifier or write amplifier.Type: GrantFiled: January 27, 1998Date of Patent: August 10, 1999Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Takahiro Sonoda, Sadayuki Morita, Hirofumi Zushi, Haruko Kawachino, Hideharu Yahata, Kenichi Fukui, Tomohiro Nagano, Masashige Harada
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Patent number: 5854562Abstract: A sense amplifier, which is intended to reduce the output response time after it has received a small voltage difference until it delivers amplified output signals, consists of a latch circuit made up of a pair of CMOS inverters, a pair of NMOS transistors connected in parallel to the latch circuit, and a current source connected in series to the latch circuit and NMOS transistor pair. The NMOS transistors amplify a small voltage difference of input signals, and the inverters of the latch circuit further amplify the resulting voltage difference to produce the output signals. Based on is a small voltage difference of input signals being amplified in two stages and the amplifying circuit being of 2-stage serial connection of the current source and the NMOS transistor or CMOS inverter, the delay time of output response can be reduced.Type: GrantFiled: April 15, 1997Date of Patent: December 29, 1998Assignees: Hitachi, Ltd, Hitachi ULSI Engineering Corp.Inventors: Hiroshi Toyoshima, Masashige Harada, Tomohiro Nagano, Yoji Nishio, Atsushi Hiraishi, Kunihiro Komiyaji, Hideharu Yahata, Kenichi Fukui, Hirofumi Zushi, Takahiro Sonoda, Haruko Kawachino, Sadayuki Morita
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Patent number: 5677887Abstract: A semiconductor static memory device, which has an increased storage capacity without imposing an increased access time, includes first, second and third metallic layers. To begin, word lines for the transfer MOSFETS are formed of the same polysilicon layer used to form the gate electrodes of the transfer MOSFETs of the memory device. A metallic layer of the first layer is used for local word lines, with the polysilicon word lines and local word lines being connected at their ends or inside of cell arrays. A metallic layer of the second layer is used for bit layers, and a metallic layer of the third layer is used for main word lines. Consequently, the word lines have a decreased time constant, allowing fast memory access. Each of sense amplifiers used in the memory device are formed with MOSFETs, which are disposed divisionally in adjacent locations. Preferably the gate electrodes of the divided MOSFETs are located symmetrically.Type: GrantFiled: March 10, 1995Date of Patent: October 14, 1997Assignees: Hitachi, Ltd., Hitachi ULSI Engineering CorporationInventors: Koichiro Ishibashi, Katsuro Sasaki, Kunihiro Komiyaji, Toshiro Aoto, Sadayuki Morita
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Patent number: 5422839Abstract: A semiconductor static memory device, which has an increased storage capacity without imposing an increased access time, includes first, second and third metallic layers. To begin, word lines for the transfer MOSFETS are formed of the same polysilicon layer used to form the gate electrodes of the transfer MOSFETs of the memory device. A metallic layer of the first layer is used for local word lines, with the polysilicon word lines and local word lines being connected at their ends or inside of cell arrays. A metallic layer of the second layer is used for bit layers, and a metallic layer of the third layer is used for main word lines. Consequently, the word lines have a decreased time constant, allowing fast memory access. Each of sense amplifiers used in the memory device are formed with MOSFETs, which are disposed divisionally in adjacent locations. Preferably the gate electrodes of the divided MOSFETs are located symmetrically.Type: GrantFiled: September 10, 1993Date of Patent: June 6, 1995Assignees: Hitachi, Ltd., Hitachi ULSI Engineering CorporationInventors: Koichiro Ishibashi, Katsuro Sasaki, Kunihiro Komiyaji, Toshiro Aoto, Sadayuki Morita
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Patent number: 5347703Abstract: A module frame work to which outfits are mounted is manufactured with high accuracy and is installed to a larger structure without adjustment operation. The module frame work comprises a pair of horizontal and mutually parallel main beams, a pair of beam members connecting the main beams, support columns vertically extending from each of junctions of the main beams with the beam members and at least a connector on an end of any of the main beams, beam members and support columns.Type: GrantFiled: March 4, 1993Date of Patent: September 20, 1994Assignee: Ishikawajima-Harima Jukogyo Kabushiki KaishaInventors: Yoshinori Imashimizu, Yoshiaki Suda, Shuichi Yamamoto, Toshiyuki Takada, Kaoru Maeyama, Etsuro Hiramoto, Toshihide Oki, Sadayuki Morita, Shoji Kawatani, Kunihito Morioka, Ryoichi Fujimitsu, Kazuhisa Handa
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Patent number: 5259332Abstract: Equipments such as outfits or plant elements are divided according to their functions. Some or all of equipments with related functions are accommodated as a module into a frame so that a plurality of frame modules are formed. The frame module is arranged in a space or the frame modules are arranged in three-dimensionally in the space.Type: GrantFiled: September 17, 1992Date of Patent: November 9, 1993Assignee: Ishikawajima-Harima Jukogyo Kabushiki KaishaInventors: Kenji Sekiguchi, Yoshinori Imashimizu, Yoshiaki Suda, Shuichi Yamamoto, Toshiyuki Takada, Tadao Yokumoto, Yoshihisa Nishimoto, Sadayuki Morita, Shinji Miura, Masanori Fukuoka, Osamu Yoshida, Kunihito Morioka, Tomohira Michishita
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Patent number: 5226583Abstract: A module frame work to which outfits are mounted is manufactured with high accuracy and is installed to a larger structure without adjustment operation. The module frame work comprises a pair of horizontal and mutually parallel main beams, a pair of beam members connecting the main beams, support columns vertically extending from each of junctions of the main beams with the beam members and at least a connector on an end of any of the main beams, beam members and support columns.Type: GrantFiled: August 14, 1991Date of Patent: July 13, 1993Assignee: Ishikawajima-Harima Jukogyo Kabushiki KaishaInventors: Yoshinori Imashimizu, Yoshiaki Suda, Shuichi Yamamoto, Toshiyuki Takada, Kaoru Maeyama, Etsuro Hiramoto, Toshihide Oki, Sadayuki Morita, Shoji Kawatani, Kunihito Morioka, Ryoichi Fujimitsu, Kazuhisa Handa